Voltage regulator
AssigneeSeiko Instruments Inc.
InventorTakashi IMURA
Life of this patent
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Abstract
Provided is a voltage regulator capable of reducing an influence of an offset to obtain an accurate output voltage. The voltage regulator includes: a first stage amplifier for amplifying and outputting a difference between a reference voltage and a divided voltage obtained by dividing a voltage output by an output transistor, to thereby control a gate of the output transistor; and a cascode amplifier circuit, in which the first stage amplifier includes: a first high breakdown voltage NMOS transistor as an input transistor; and an NMOS transistor as a tail current source, and in which the cascode amplifier circuit includes a second high breakdown voltage NMOS transistor as a cascode transistor.
Claims1
A voltage regulator, comprising:
- a first stage amplifier for amplifying and outputting a difference between a reference voltage and a divided voltage obtained by dividing a voltage output by an output transistor, to thereby control a gate of the output transistor;
- and
- a cascode amplifier circuit,
- wherein the first stage amplifier comprises:
- a first high breakdown voltage NMOS transistor as an input transistor;
- and
- an NMOS transistor as a tail current source, and
- wherein the cascode amplifier circuit comprises a second high breakdown voltage NMOS transistor as a cascode transistor.
Dependencies are inferred from the claim text.