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US 2013/0174147 A1Published application
Low Latency Virtual Machine Page Table Management
AssigneeIntel Corporation
InventorsRavi L. Sahita, David M. Durham, Gilbert Neiger, Andrew V. Anderson, Scott D. Rodgers
Life of this patent
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Abstract
Various embodiments of this disclosure may describe method, apparatus and system for reducing system latency caused by switching memory page permission views between programs while still protecting critical regions of the memory from attacks of malwares. Other embodiments may be disclosed and claimed.
Claims3
A processor, comprising:
- instruction hardware to receive a view switch instruction;
- and
- execution hardware to execute a view switch instruction.
A method, comprising:
- receiving, by a processor, a view switch instruction;
- and
- executing, by a processor, a view switch instruction.
A system, comprising:
- memory;
- and
- a processor including
- instruction hardware to receive a view switch instruction, and
- execution hardware to execute a view switch instruction.
2 more elements
Dependencies are inferred from the claim text.