Floorplan estimation
AssigneeArteris, Inc.
InventorsJean-Jacques Lecler, Boris Boutillier
Life of this patent
Estimating the term…
Abstract
The disclosed invention gives an estimation of the placement location of the units comprising a NoC within the floorplan of a chip. From that, and with knowledge of the number of wires of links within the NoC topology, an estimation of the wire density at each point is calculated. Furthermore, an estimate is made of the locations of the critical timing paths within the chip. The timing path calculation is also used to generate IO constraints for the synthesis of modules comprising different parts of the NoC. Further still, a scenario of traffic through the NoC is combined with the wire map and information about the width of links within the topology to generate an estimation of power consumption.
Claims32
One or more non-transitory computer readable media for storing computer-executable instructions that, when executed by a processor, cause the processor to perform a method for presenting a network-on-chip within the floorplan, which includes a plurality of points, of a semiconductor chip, the method comprising the steps of:
- receiving a shape of at least one agent including at least one point selected from the plurality of points of the floorplan;
- receiving a size of at least one unit;
- determining a table of connectivity between a plurality of nodes;
- and
- calculating a shape, which includes at least one point selected from the plurality of points of the floorplan, for the at least one unit, such that the total distance between each point of a node selected from the plurality of nodes and each point of at least one connected node, which is selected from the plurality of nodes and defined by the table, is minimized.
A method of designing a network on chip, the method comprising:
- determining a topology;
- determining a floorplan;
- estimating the placement of a plurality nodes within the floorplan;
- and
- modifying the topology in order to improve the placement of the plurality of nodes.
A system including:
- at least one processor;
- and
- at least one memory unit in communication with the at least one processor, the at least one memory unit includes at least one computer program code and the at least one memory unit and the at least one computer program code, with the at least one processor, cause the system to present a network-on-chip within a floorplan, which includes a plurality of points, of a semiconductor chip through performing steps including:
- receiving a first node's shape and size, wherein the first node is selected from a plurality of nodes and includes at least one point selected from the plurality of points of the floorplan;
- receiving a second node's size, wherein the second node is selected from the plurality of nodes;
- determining a table of connectivity between the plurality of nodes, wherein the table represents the connection between the plurality of nodes including the first node and the second node connectivity information;
- and
- calculating the second node's shape, which includes at least one point selected from the plurality of points of the floorplan, such that the total distance between each point of the first node and each point the second node is minimized.
Dependencies are inferred from the claim text.