Method of generating a bias-adjusted layout design of a conductive feature and method of generating a simulation model of a predefined fabrication process
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChia-Ming HO, Ke-Ying SU, Hsiao-Shu CHAO, Yi-Kan CHENG
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Abstract
A method of generating a bias-adjusted layout design of a conductive feature includes receiving a layout design of the conductive feature. If a geometry configuration of the layout design is within a first set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a first layout bias rule. If the geometry configuration of the layout design is within a second set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a second layout bias rule.
Claims19
A method of generating a bias-adjusted layout design of a conductive feature, the conductive feature being a portion of an integrated circuit, the method comprising:
- receiving a layout design of the conductive feature;
- determining, by a hardware processor, if a geometry configuration of the layout design of the conductive feature is within a first set of predetermined criteria or a second set of predetermined criteria different from the first set of predetermined criteria;
- generating the bias-adjusted layout design of the conductive feature according to a first layout bias rule after a determination that the geometry configuration of the layout design of the conductive feature is within the first set of predetermined criteria;
- and
- generating the bias-adjusted layout design of the conductive feature according to a second layout bias rule different from the first layout bias rule after a determination that the geometry configuration of the layout design of the conductive feature is within the second set of predetermined criteria.
A method of generating a simulation model of a predefined fabrication process according to a sample conductive feature, the method comprising:
- receiving a geometry configuration of the sample conductive feature;
- generating a circuit-level simulation model of the sample conductive feature based on the geometry configuration of the sample conductive feature;
- converting, by a hardware processor, the circuit-level simulation model of the sample conductive feature into at least (1) a first layout bias rule corresponding to a first set of predetermined criteria of the layout design and (2) a second layout bias rule, different from the first layout bias rule, corresponding to a second set of predetermined criteria of the layout design.
A computer system comprising:
- a non-transitory computer readable storage medium encoded with a computer program code;
- and
- a processor coupled to the computer readable storage medium, the processor being configured to execute the computer program code, the computer program code being arranged to cause the processor to:
- receive a layout design of a conductive feature, the conductive feature being a portion of an integrated circuit to be manufactured by a predefined fabrication process;
- determine if a geometry configuration of the layout design of the conductive feature is within a first set of predetermined criteria or a second set of predetermined criteria different from the first set of predetermined criteria;
- generate a bias-adjusted layout design of the conductive feature according to a first layout bias rule after determining that the geometry configuration of the layout design of the conductive feature falls within the first set of predetermined criteria;
- and
- generate the bias-adjusted layout design of the conductive feature according to a second layout bias rule different from the first layout bias rule after determining that the geometry configuration of the layout design of the conductive feature falls within the second set of predetermined criteria.
Dependencies are inferred from the claim text.