US 2013/0174109 A1 · DEVICE MISMATCH CORNER MODEL

Abstract

A device mismatch corner model for semiconductor device simulation is provided. A method of providing the device mismatch corner model for semiconductor device simulation, includes selecting a type of electric performance target F for a type of device, determining a number N of semiconductor devices for which mismatches among electric performance targets of the semiconductor devices are simulated, and determining a desired k-sigma mismatch corner value among N(N−1)/2 pairs of the electric performance targets. The method further includes identifying at least one electric parameter P of the semiconductor devices that has a mismatch component and contributes to the mismatches among the electric performance targets of the semiconductor devices, determining a plurality of corner values for the at least one electrical parameter P, and running at most N circuit simulations based on the determined plurality of corner values which are recalculated for each of the circuit simulations.

Claims25

Dependent claims

A method of providing a device mismatch corner model for semiconductor device simulation, comprising:

selecting a type of electric performance target F for a type of device;
determining a number N of semiconductor devices for which mismatches among electric performance targets of the semiconductor devices are simulated;
determining a desired k-sigma mismatch corner value among N(N−1)/2 pairs of the electric performance targets;
identifying at least one electric parameter P of the semiconductor devices that has a mismatch component and contributes to the mismatches among the electric performance targets of the semiconductor devices;
determining a plurality of corner values for the at least one electrical parameter P;
running at most N circuit simulations based on the determined plurality of corner values which are recalculated for each of the circuit simulations;
and
post-processing results of the N circuit simulations to achieve simultaneous mismatch among N(N−1)/2 pairs of the electric performance targets,
wherein at least the step of the running at most N circuit simulations is implemented on a processor.

6 more elements

A method for semiconductor device simulation, comprising:

determining a number N of semiconductor devices which have mismatch in at least three respective parameters;
determining a plurality of corner values for the at least three respective parameters;
and
running (N−1) circuit simulations based on the determined plurality of corner values which are recalculated for each of the circuit simulations,
wherein at least the step of the running (N−1) circuit simulations is implemented on a processor;
and
the plurality of corner values is determined based on the following equation:
Pi,l=μ+sσcm+kσm0ti,l,i=1,2,3, . . . ,N,l=1,2,3, . . . ,N−1,
where i is an ith device of the semiconductor devices, l is a lth circuit simulation of the (N−1) circuit simulations, μ is a predetermined mean value for the at least three parameters, s is a corner value for chip mean part of variations, σcm is a standard deviation for chip mean part of variations, k is a desired mismatch corner value among electric performance targets F1, F2, . . . , FN, σm0 is a standard deviation for mismatch part of variations, and ti,l is a plurality of mismatch corner values.

6 more elements

A computer system for providing a device mismatch corner model for semiconductor device simulation, the system comprising:

a CPU, a computer readable memory and a tangible computer readable storage media;
first program instructions to determine a number N of semiconductor devices which have mismatch in at least three respective parameters;
second program instructions to determine a plurality of corner values for the at least three respective parameters based on the number N of the semiconductor devices;
third program instructions to run (N−1) or N circuit simulations based on the determined plurality of corner values which are recalculated for each of the circuit simulations, and based on user input;
and
fourth program instructions to process one or more results of the at most N circuit simulations to determine one or more worst-case effects of the mismatch of the semiconductor devices,
wherein:
the first, second, third, and fourth program instructions are stored on the tangible computer readable storage media for execution by the CPU via the computer readable memory;
and
the plurality of corner values is determined for (N−1) circuit simulations based on the following equation:
Pi,l=μ+sσcm+kσm0ti,l,i=1,2,3, . . . ,N,l=1,2,3, . . . ,N−1,
where i is an ith device of the semiconductor devices, l is a lth circuit simulation of the (N−1) circuit simulations, μ is a predetermined mean value for the at least three parameters, s is a corner value for chip mean part of variations, Gcm is a standard deviation for chip mean part of variations, k is a desired mismatch corner value among electric performance targets F1, F2, FN, σm0 is a standard deviation for mismatch part of variations, and til is a plurality of mismatch corner values for the (N−1) circuit simulations;
and
the plurality of corner values is determined for N circuit simulations based on the following equation:
Pi,l=μ+sσcm+kσm0ui,l,i,l=1,2,3, . . . ,N,
where l is an lth circuit simulation of the N circuit simulations, and ui,l is a plurality of mismatch corner values for the N circuit simulations.

13 more elements

Dependencies are inferred from the claim text.

Device mismatch corner model

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Device mismatch corner model

Life of this patent

Abstract

Claims25