Stitch and trim methods for double patterning compliant standard cell design

A system, comprising:

• a computer readable storage medium containing data identifying a plurality of circuit components to be included in an integrated circuit (“IC”) layout;
• and
• a processor coupled to read the storage medium, the processor configured to:
• provide the persistent machine readable storage medium encoded with data representing a plurality of cell layouts having a plurality of patterns, the patterns including a power bus pattern (“Vdd bus”) and a ground bus pattern (“Vss bus”), wherein the cell layouts are capable of being assigned into respective sets to be patterned using at least a first mask and a second mask to pattern a single layer wherein the plurality of cell layouts include a layout of a first cell and layout of a second cell having respective stitches in the Vdd or Vss bus near a first corner and a second corner of the first cell and near a first corner and a second corner of the second cell;
• arranging instances of the first and second cells horizontally so as to have an abutting Vdd or Vss bus at the second corner of the first cell and the first corner of the second cell;
• removing a respective stitch from near the second corner of the first cell and from near the first corner of the second cell, while keening the stitches near the first corner of the first cell and the second corner of the second cell.

A computer readable storage medium encoded with computer code such that, when the computer code is executed by a processor, the processor performs a method comprising:

• receiving an identification of a plurality of circuit components to be included in an integrated circuit (“IC”) layout;
• providing a persistent machine readable storage medium encoded with data representing a plurality of cell layouts having a plurality of patterns, the patterns including a power bus pattern (“Vdd bus”) and a ground bus pattern (“Vss bus”), wherein the cell layouts are capable of being assigned into respective sets to be patterned using at least a first mask and a second mask for patterning a single layer wherein the plurality of cell layouts include a first cell and a layout of a second cell having respective stitches in the Vdd or Vss bus near a first corner and a second corner of the first cell and near a first corner and a second corner of the second cell;
• arranging instances of the first and second cells horizontally so as to have an abutting Vdd or Vss bus at the second corner of the first cell and the first corner of the second cell;
• removing a respective stitch from near the second corner of the first cell and from near the first corner of the second cell, while keeping the stitches near the first corner of the first cell and the second corner of the second cell;
• and
• outputting the IC layout to a machine readable storage medium to be read by a system for controlling a process to fabricate a plurality of masks for patterning a single layer of a semiconductor substrate.