Placement aware clock gate cloning and fanout optimization

Abstract

Gating clocks has been a widely adopted technique for reducing dynamic power. The clock gating strategy employed has a huge bearing on the clock tree synthesis quality along with the impact to leakage and dynamic power. This invention is a technique for clock gate optimization to aid the clock tree synthesis. The technique enables cloning and redistribution of the fanout among the existing equivalent clock gates. The technique is placement aware and hence reduces overall clock wire length and area. The technique involves employing the k-means clustering algorithm to geographically partition the design's registers. This invention improves the clock tree synthesis quality on a complex design.

Dependencies are inferred from the claim text.