Mixed Domain FFT-Based Non-Binary LDPC Decoder
AssigneeLSI Corporation
InventorsLei Chen, Zongwang Li, Johnson Yen, Shaohua Yang
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Abstract
Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for decoding data in a mixed domain FFT-based non-binary LDPC decoder. For example, in one embodiment an apparatus includes a message processing circuit operable to process variable node messages and check node messages in a log domain, and a check node calculation circuit in the low density parity check decoder operable to perform a Fast Fourier Transform-based check node calculation in a real domain. The message processing circuit and the check node calculation circuit perform iterative layer decoding.
Claims20
An apparatus for decoding of low density parity check encoded data comprising:
- a message processing circuit in a low density parity check decoder operable to process variable node messages and check node messages in a log domain;
- and
- a check node calculation circuit in the low density parity check decoder operable to perform a Fast Fourier Transform-based check node calculation in a real domain, wherein the message processing circuit and the check node calculation circuit are operable to perform iterative layer decoding.
A method of decoding data in a mixed domain low density parity check decoder, comprising:
- processing variable node messages and check node messages in the mixed domain low density parity check decoder in a log domain;
- transforming variable node messages from the log domain to a real domain;
- perform Fast Fourier Transform-based check node calculations in the real domain to yield real domain check node messages, wherein the processing and the check node calculations comprise iterative layer decoding;
- and
- transforming the real domain check node messages from the real domain to the log domain.
A storage system comprising:
- a storage medium maintaining a data set;
- a write head operable to magnetically record the data set to the storage medium;
- and
- a mixed domain low density parity check decoder operable to perform layered decoding, comprising:
- a message processing circuit operable to process variable node messages and check node messages in a log domain;
- and
- a check node calculation circuit operable to perform a Fast Fourier Transform-based check node calculation in a real domain.
Dependencies are inferred from the claim text.