Multiple input and/or output data for boundary scan nodes
OwnerHiroyuki Sasaya, Supatra Basuinventors
Life of this patent
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Abstract
A boundary scan node of a boundary scan chain for testing an associated node of core logic core logic includes a first boundary scan cell having an input that is coupled to a first data output of the core logic. A second boundary scan cell having an output is coupled to a first data input of the core logic. A programmable series connection is arranged to selectively couple an output of the first boundary scan cell to an input of the second boundary scan cell when the boundary scan node is arranged in an internal test mode for the core logic. Test stimulus can be written to the boundary scan node using a data register clock and test results can be read from the boundary scan node using the data register clock.
Claims20
A boundary scan node for scan chain testing of a core logic, comprising:
- a first boundary scan cell having an input that is coupled to a first data output of the core logic;
- a second boundary scan cell having an output that is coupled to a first data input of the core logic;
- and
- a multiplexor that is arranged to couple a programmable series connection from an output of the first boundary scan cell to an input of the second boundary scan cell when the boundary scan node is arranged in an internal test mode for the core logic.
An electronic system having a self-test capability, comprising:
- core logic that is arranged to perform an internal test in response to stimulus data;
- and
- a boundary scan chain node having a first boundary scan cell having an input that is coupled to a first data output of the core logic, a second boundary scan cell having an output that is coupled to a first data input of the core logic;
- and a programmable series connection from an output of the first boundary scan cell to an input of the second boundary scan cell when the boundary scan node is arranged in an internal test mode for the core logic.
A method of conveying multiple data in a boundary scan node testing of core logic, comprising:
- coupling an input of a first boundary scan cell to a first data output of the core logic;
- coupling an output of a second boundary scan cell to a first data input of the core logic;
- and
- selectively coupling a programmable series connection from an output of the first boundary scan cell to an input of the second boundary scan cell when the boundary scan node is arranged in an internal test mode for the core logic.
Dependencies are inferred from the claim text.