High density flip-flop with asynchronous reset

An electronic system having a self-test capability, comprising:

• operational circuitry arranged on a substrate for performing a software application;
• a clock generator for generating a clock signal to synchronize the operational circuitry;
• and
• a plurality of scan flip-flops that are arranged in the substrate to provide test stimulus to and read test results from the operational circuitry, wherein each scan flip-flop includes an output that is coupled to an input of an adjacent scan flip-flop, and wherein each scan flip-flop includes:
• an input stage that is arranged to alternately pass or block a data input signal in response to the clock signal and a gated clock signal that is gated by an asynchronous clear signal such that the gated clock signal is the inverse of the clock signal when the asynchronous clear signal is not asserted and the gated clock signal is not active when the asynchronous clear signal is asserted;
• a master latch coupled to receive and to latch the passed data signal in a latched state, arranged to maintain the latched state at a node of the master latch in response to a feedback path internal to the master latch and to clear the latched state in response to the asynchronous clear signal being asserted, and is arranged to generate a master latch output signal in response to the latched state of the master latch;
• and
• a slave latch coupled to receive and to latch the master latch output signal in a latched state and wherein the slave latch is arranged to asynchronously receive the cleared latched state in response to the asynchronous clear signal being asserted.

A method of latching in a master/slave flip-flop, comprising:

• generating a gated clock signal that is gated by an asynchronous clear signal such that the gated clock signal is the inverse of a clock signal when the asynchronous clear signal is not asserted and the gated clock signal is not active when the asynchronous clear signal is asserted;
• applying the gated clock signal to a first transistor network of a first type in a feedback loop in a master latch of the master/slave flip-flop and to a second transistor network of a second type in a feedback loop in a slave latch of the master/slave flip-flop;
• applying the gated clock signal to a first transistor network of a second type in the feedback loop in the master latch of the master/slave flip-flop and to a second transistor network of the second type in the feedback loop in the slave latch of the master/slave flip-flop;
• and
• asynchronously clearing the latched state of the master latch in response to the asynchronous clear signal being asserted and using the cleared latched state of the master latch to asynchronously set the state of the slave latch.