Computer memory test structure
AssigneeSilicon Image, Inc.
InventorsChinsong Sul, Sungjoon Kim
Life of this patent
Estimating the term…
Abstract
A method and apparatus for a computer memory test structure. An embodiment of a method for testing of a memory board includes testing a memory of the memory board, where testing the memory including use of a built-in self-test structure to provide a first test pattern for the memory. The method further includes testing an IO (input output) interface of the memory with a host, where testing of the IO interface includes use of the built-in self-test structure to provide a second test pattern for the IO interface.
Claims29
A method of testing a memory board comprising:
- testing a memory of the memory board, testing of the memory including use of a built-in self-test structure to provide a first test pattern for the memory;
- and
- testing an IO (input output) interface of the memory with a host, testing of the IO interface including use of the built-in self-test structure to provide a second test pattern for the IO interface.
An apparatus including:
- a memory, the memory including a first test structure;
- a physical layer of a host, the physical layer includes a second test structure;
- and
- an interface between the memory and the physical layer;
- wherein the memory and the interface are to be tested using the first test structure and the second test structure.
A computer-readable medium having stored thereon data representing sequences of instructions that, when executed by a processor, cause the processor to perform operations comprising:
- testing a memory of serial port dynamic random access memory (SPDRAM) board, testing of the memory including use of a built-in self-test structure to provide a first test pattern for the memory;
- and
- testing an IO (input output) interface of the memory with a host, testing of the IO interface including use of the built-in self-test structure to provide a second test pattern for the IO interface, wherein the testing of the memory is separate from the testing of the IO interface.
Dependencies are inferred from the claim text.