Device
AssigneeElpida Memory, Inc.
InventorIchiro ABE
Life of this patent
Estimating the term…
Abstract
A device includes memory banks, each having a plurality of memory cells with respective error data output circuits. Each of the error data output circuits outputs first to M-th (M is an integer of 2 or more) error data according to first to M-th data retrieved from first to M-th memory cell groups selected from its corresponding memory bank. A test control circuit has first error data synthesis circuits and second to (M+1)-th error data synthesis circuits, each of which synthesizes the first to M-th error data from a corresponding error data output circuit and outputs the synthesized data as first test data. Each of the error data synthesis circuits synthesizes m-th (m is an integer of from 1 to M) error data from the error data output circuits and outputs the synthesized data as (m+1)-th test data.
Claims16
A device comprising:
- a plurality of memory banks each having a plurality of memory cells;
- a plurality of error data output circuits provided in correspondence with the respective memory banks, each of the error data output circuits outputting first to M-th (M is an integer of 2 or more) error data according to first to M-th data retrieved from first to M-th memory cell groups selected from its corresponding memory bank;
- and
- a test control circuit having a plurality of first error data synthesis circuits each of which synthesizes the first to M-th error data from the corresponding one of the error data output circuits and outputs the synthesized data as first test data, and second to (M+1)-th error data synthesis circuits each of which synthesizes m-th (m is an integer of from 1 to M) error data from the error data output circuits and outputs the synthesized data as (m+1)-th test data.
A device comprising:
- a plurality of memory banks each having first to M-th (M is an integer of 2 or more) sub memory banks;
- a plurality of error data output circuits provided in correspondence with the respective memory banks, and including first to M-th error detection circuits respectively corresponding to the first to M-th sub memory banks in the corresponding memory banks;
- a plurality of first synthesis circuits respectively provided in correspondence with the plurality of error data output circuits to synthesize error data from the first to M-th error detection circuits of the corresponding error data output circuit;
- and
- second to (M+1)-th synthesis circuits each of which synthesizes error data respectively from all the m-th (m is an integer of 1 to M) error detection circuits included in the plurality of error data output circuits.
The device according to 11, further comprising a plurality of read/write amplifiers respectively provided in correspondence with the first to M-th sub memory banks of the plurality of memory banks, wherein:
- in a normal operation mode, data retrieved from the sub memory banks are supplied to the parallel-serial conversion circuit via the corresponding read/write amplifiers;
- and
- in a test mode, data retrieved from the sub memory banks are supplied to the corresponding error detection circuits, and the error data are supplied from the error detection circuits to the parallel-serial conversion circuit.
A method of operating a device including a first memory area designated by a first memory area selection information and a second memory area designated by a second memory area selection information, each of the first and second memory areas including a first memory block designated by a first memory block selection information and a second memory block designated by a second memory block selection information, the method comprising:
- reading a first information stored in a memory cell in the first memory block of the first memory area, designated by the first memory area selection information and the first memory block selection information;
- reading a second information stored in a memory cell in the second memory block of the first memory area, designated by the first memory area selection information and the second memory block selection information;
- reading a third information stored in a memory cell in the first memory block of the second memory area, designated by the second memory area selection information and the first memory block selection information;
- reading a fourth information stored in a memory cell in the second memory block of the second memory area, designated by the second memory area selection information and the second memory block selection information;
- synthesizing the first and second information to produce a first data;
- synthesizing the third and forth information to produce a second data;
- synthesizing the first and third information to produce a third data;
- and
- synthesizing the second and forth information to produce a fourth data.
Dependencies are inferred from the claim text.