Boundary scan chain for stacked memory
AssigneeIntel Corporation
InventorDavid J. Zimmerman
Life of this patent
Estimating the term…
Abstract
A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain.
Claims31
A memory device comprising:
- a system element;
- and
- a memory stack including one or more memory die layers, each memory die layer including a plurality of input-output (I/O) cells and a boundary scan chain for the I/O cells;
- wherein a boundary scan chain of a memory die layer includes:
- a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including:
- a first scan logic multiplexer;
- and
- a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and
- a decoder to provide command signals to the scan chain.
A method comprising:
- inputting a set of scan data to a first memory element of a plurality of memory elements of a memory stack, wherein each memory element includes a scan boundary chain;
- transferring the scan data to a second memory element of the plurality of memory elements;
- obtaining an output of scan data from the second memory element;
- and
- determining if the scan data input to the first memory element matches the scan data output from the second memory element, wherein a scan test is successful if the scan data input and the scan data output match.
A system comprising:
- a processor to process data for the system;
- a transmitter to transmit data, a receiver to receive data, or both via an omnidirectional antenna;
- a memory to store data for the system, the memory including a stacked memory, the stacked memory including a memory stack of one or more memory elements, wherein each memory element a boundary scan chain for a plurality of I/O cells of the memory element;
- wherein a boundary scan chain of a memory element includes:
- a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer and a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and
- a decoder to provide command signals to the scan chain.
A non-transitory computer-readable storage medium having stored thereon data representing sequences of instructions that, when executed by a processor, cause the processor to perform operations comprising:
- inputting a set of scan data to a first memory element of a plurality of memory elements of a memory stack, wherein each memory element includes a scan boundary chain;
- transferring the scan data to a second memory element of the plurality of memory elements;
- obtaining an output of scan data from the second memory element;
- and
- determining if the scan data input to the first memory element matches the scan data output from the second memory element, wherein a scan test is successful if the scan data input and the scan data output match.
A semiconductor device comprising:
- a controller die;
- and
- a memory die coupled with the controller die, the memory die including a plurality of input-output (I/O) cells, each I/O cell including normal logic and scan logic, the scan logic including,
- a first scan logic multiplexer, the first scan logic multiplexer including a first input from an I/O cell and a second input from one of another I/O cell or a serial data input, and
- a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, the scan logic latch having an output to one of a third I/O cell or a serial data output;
- and
- a decoder located on the memory die, the decoder to provide command signals to the scan chain.
Dependencies are inferred from the claim text.