Memory device with background built-in self-testing and background built-in self-repair
AssigneeMoSys, Inc.
InventorsBendik Kleveland, Dipak K. Sikdar, Rajesh Chopra, Jay Patel
Life of this patent
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Abstract
A memory device with background built-in self-testing (BBIST) includes a plurality of memory blocks; a memory buffer to offload data from one of the plurality of memory blocks temporarily; and a memory block stress controller to control a stress test applied to the one of the memory blocks when the data is temporarily offloaded on the memory buffer. The stress test tests for errors in the one of the plurality of the memory blocks.
Claims85
An integrated circuit device (IC) comprising:
- a main memory comprising a plurality of memory cells;
- a temporary memory;
- a background built-in self-test module (BBISTM) configured to select a portion of the main memory as the target memory under test (TMUT), to cache data from the TMUT into the temporary memory, and to apply a test to the TMUT;
- and
- wherein the BBISTM is operational simultaneously while the IC is operational for performing external accesses during field operation.
A method of testing a memory of an integrated circuit device, the method comprising:
- selecting a portion of a memory as a target memory under test (TMUT);
- operating a test on the TMUT;
- operating at least a portion of the memory outside of the test;
- and
- wherein the operating of the test and the operating at least a portion of the memory outside of the test occur at approximately the same time.
An integrated circuit device (IC) comprising:
- a main memory;
- a temporary memory;
- a redundant memory;
- a background built-in self-test module (BBISTM) configured to select a portion of the main memory as the target memory under test (TMUT), to cache data from the TMUT into the temporary memory, and to apply a test to the TMUT, wherein the BBISTM is operational simultaneously while the IC is operational for performing external accesses during field operation;
- and
- a background built-in self-repair module (BBISRM) configured to repair the TMUT by storing the cached data into a selected portion of the redundant memory block, and mapping a memory address of the TMUT to the selected portion of the redundant memory block.
An integrated circuit device (IC) comprising:
- a main memory;
- a temporary memory;
- a global bit registry (GBR);
- a background built-in self-test module (BBISTM) configured to select a portion of the main memory as the target memory under test (TMUT), to cache data from the TMUT into the temporary memory, and to apply a test to the TMUT, wherein the BBISTM is operational simultaneously while the IC is operational for performing external accesses during field operation;
- and
- a background built-in self-repair module (BBISRM) configured to identify a weak bit of the TMUT that is susceptible to a spurious data error, write a memory address of the TMUT into the GBR as a global memory address, write a bit identifier of the weak bit into the GBR, and store a correct bit value of the weak bit into the GBR so that the bit identifier of the weak bit and the correct bit value of the weak bit is associated with the global memory address.
A method of repairing a memory of an integrated circuit device, the method comprising:
- selecting a portion of the main memory as a target memory under test (TMUT);
- caching data from the TMUT into a temporary memory;
- determining the TMUT is to be replaced;
- and
- replacing the TMUT by storing the cached data into a selected portion of a redundant memory block, and mapping a memory address of the TMUT to the selected portion of the redundant memory block.
A method of repairing a memory of an integrated circuit device, the method comprising:
- selecting a portion of the main memory as a target memory under test (TMUT);
- caching data from the TMUT into a temporary memory;
- identifying a weak bit of the TMUT that is susceptible to a spurious data error;
- writing the memory address of the TMUT into a CGBR as a global memory address;
- writing a bit identifier of the weak bit into the GBR;
- and
- writing a correct bit value of the weak bit into the GBR so that the bit identifier of the weak bit and the correct bit value of the weak bit is associated with the global memory address.
Dependencies are inferred from the claim text.