Memory controller and memory access system
AssigneePanasonic Corporation
InventorsHisataka NAKABAYASHI, Miho TAKEDA, Masanori ITO
Life of this patent
Estimating the term…
Abstract
A controller section outputs a first signal and a second signal holding a phase relationship with the first signal. The second signal is received by a memory I/F section via a FIFO memory of an error detecting section. The memory I/F section performs timing adjustment for the first and second signals, outputs the first and second signals after the timing adjustment to a memory, and loops back the second signal. A data comparator compares the looped-back second signal with the original second signal outputted from the FIFO memory and corresponding to the looped-back signal.
Claims8
A memory controller which performs data input/output with a memory, comprising:
- a controller section configured to transmit/receive data to/from circuit blocks and generate and output a first signal and a second signal holding a predetermined phase relationship with the first signal;
- an error detecting section having a FIFO memory configured to receive as an input the second signal outputted from the controller section;
- and
- a memory I/F section configured to receive as inputs the first signal outputted from the controller section and the second signal outputted from the FIFO memory of the error detecting section, perform timing adjustment for the first and second signals, and output the first and second signals after the timing adjustment to the memory,
- wherein
- the second signal outputted from the memory I/F section is outputted to the memory and is looped back to the error detecting section, and
- the error detecting section includes a data comparator configured to compare the looped-back second signal with the original second signal outputted from the FIFO memory and corresponding to the looped-back second signal.
Dependencies are inferred from the claim text.