Hs-can bus clock recovery using a tracking oscillator circuit
AssigneeSTMicroelectronics R&D (Shanghai) Co. Ltd.
InventorsPanny Cai, Martin Huag
Life of this patent
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Abstract
A method for recovering a clock frequency of a CAN bus, the method including: receiving a data signal, wherein the data signal includes at least one state transition; detecting the state transition; and adjusting a frequency of a clocking signal generated by an oscillator circuit, wherein the frequency is adjusted when the state transition is detected and adjusting the frequency is for recovering the clock frequency of the CAN bus.
Claims15
A method for recovering a clock frequency of a CAN bus, the method comprising:
- receiving a data signal, wherein the data signal comprises at least one state transition;
- detecting the state transition;
- and
- adjusting a frequency of a clocking signal generated by an oscillator circuit, wherein the frequency is adjusted when the state transition is detected and adjusting the frequency is for recovering the clock frequency of the CAN bus.
A tracking oscillator circuit configured to recover a clock frequency of a bus, the device comprising:
- an edge detector circuit for detecting state transitions of a received data signal;
- and
- an oscillator core circuit configured to generate an internal oscillator of a first frequency wherein the first frequency is synchronized with a second frequency of the received data signal.
A CAN bus system, comprising:
- a CAN bus which couples a master device to at least one slave device;
- the master device comprising;
- a clock generator adapted to provide a clock frequency for the CAN bus;
- and
- a sending device adapted to send data, having the clock frequency, via the CAN bus;
- the at least one slave device comprising:
- a receiver for receiving the data on the bus;
- and
- a tracking oscillator circuit configured to recover a clock frequency of the bus, the tracking oscillator circuit comprising:
- an edge detector circuit for detecting state transitions of a received data signal;
- and
- an oscillator core circuit configured to generate internal oscillator of a first frequency wherein the first frequency is synchronized with a second frequency of the received data signal.
Dependencies are inferred from the claim text.