Multi-processor computer systems and methods
OwnerRaphael Gay, Robert J. Horninginventors
Life of this patent
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Abstract
Multi-processor computer systems and methods are provided. A multi-processor computer system can include a plurality of communicatively coupled processors (1101-N), each coupled to a common motherboard (120) and each associated with a memory (1401-N). The system can include a boot code (130) executable from at least one of a standard mode and an independent mode. The plurality of communicatively coupled processors can execute one instance of the boot code in standard mode and at least a portion of the plurality of communicatively coupled processors can execute one instance of the boot code in independent mode.
Claims15
A multi-processor computer system (100), comprising:
- a plurality of communicatively coupled (160) processors (1101-N):
- each coupled to a common motherboard (120), and
- each associated with a memory (1401-N);
- and
- a boot code (130), the boot code executable from at least one of a standard mode and an independent mode;
- wherein the plurality of communicatively coupled processors execute one instance of the boot code in standard mode;
- and
- wherein at least a portion of the plurality of communicatively coupled processors execute one instance of the boot code in independent mode.
A multi-processor computer method, comprising:
- entering (310) an independent mode;
- retrieving (320) a first boot code from a first boot code storage device;
- executing (330) the first boot code on a first group of processors selected from a plurality of processors coupled to a motherboard;
- retrieving (340) a second boot code from a second boot code storage device;
- and
- contemporaneously executing (350) the second boot code on a second group of processors selected from the plurality of processors coupled to the motherboard.
A multi-processor computer system, comprising:
- two communicatively coupled processors (110), each coupled to a common motherboard (120);
- a first boot code (130);
- a first memory (140) accessible to a first (1101) of the two communicatively coupled processors;
- the two communicatively coupled processors configured to execute one instance of the first boot code when in a standard mode;
- a first input/output (I/O) controller (170), couplable to the two communicatively coupled processors when in the standard mode;
- a partitioning module (210), the partitioning module including:
- a second boot code (220) and a second input/output controller (230), couplable to the second processor when in the independent mode;
- the second of the two communicatively coupled processors configured to execute one instance of the second boot code when in an independent mode;
- and
- a user interface (240) to permit a user to reversibly alternate between at least one of the standard mode or the independent mode.
Dependencies are inferred from the claim text.