Processor with Hazard Tracking Employing Register Range Compares
AssigneeQUALCOMM Incorporated
InventorsKenneth Alan Dockser, Yusuf Cagatay Tekmen
Life of this patent
Estimating the term…
Abstract
Systems and methods for tracking data hazards in a processor. The processor comprises a pipelined architecture configured to execute a first instruction and a second instruction, wherein the second instruction is older than the first instruction. At least one of the first and second instructions comprises at least one operand expressed as a range of registers. Hazard detection logic is configured to compare the first instruction and the second instruction to determine if there is a data hazard, prior to expanding the second instruction.
Claims24
A method for tracking data hazards in a processor comprising:
- tracking a first instruction;
- and
- comparing the first instruction to a second instruction to determine if there is a data hazard, prior to expanding the second instruction.
A processor comprising:
- a pipelined architecture configured to execute a first and a second instruction;
- and
- a hit detection logic for comparing the first instruction to the second instruction to determine if there is a data hazard, prior to expanding the second instruction.
A processing system for tracking data hazards in a processor comprising:
- means for tracking a first instruction;
- and
- means for comparing the first instruction to a second instruction to determine if there is a data hazard, prior to expanding the second instruction.
A non-transitory computer-readable storage medium comprising code, which, when executed by a processor, causes the processor to perform operations for tracking data hazards in the processor, the non-transitory computer-readable storage medium comprising:
- code for tracking a first instruction;
- and
- code for comparing the first instruction to a second instruction to determine if here is a data hazard, prior to expanding the second instruction.
Dependencies are inferred from the claim text.