Processor and Methods of Adjusting a Branch Misprediction Recovery Mode
AssigneeAdvanced Micro Devices, Inc.
InventorsYasuko Watanabe, Srilatha Manne, Trivikram Krishnamurthy, Rajani Pai, Michael Schulte
Life of this patent
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Abstract
A processor core includes a fetch control unit for fetching instructions and placing the instructions into an instruction queue and includes a branch predictor for controlling the fetch control unit to speculatively fetch at least one instruction subsequent to an unresolved branch instruction. The processor further includes a controller configured to dispatch instructions from the instruction queue and, in response to a branch misprediction of an unresolved control instruction, to apply a selected one of a checkpointing-based recovery mode and a commit-time-based recovery mode.
Claims20
A processor core comprising:
- a fetch control unit for fetching instructions and placing the instructions into an instruction queue;
- a branch predictor for controlling the fetch control unit to speculatively fetch at least one instruction subsequent to an unresolved branch instruction;
- and
- a controller configured to dispatch instructions from the instruction queue and, in response to a branch misprediction of an unresolved control instruction, to apply a selected one of a checkpointing-based recovery mode and a commit-time-based recovery mode.
A method comprising:
- fetching instructions of an instruction stream for execution on a processor having one or more cores including an unresolved branch instruction and at least one speculative instruction;
- detecting a branch misprediction of the unresolved branch instruction;
- and
- applying a selected one of a checkpointing-based recovery mode and a commit-time-based recovery mode in response to detecting the branch misprediction.
A multi-core processor comprising:
- a fetch control unit for fetching instructions and placing the instructions into an instruction queue;
- a branch predictor for controlling the fetch control unit to speculatively fetch instructions corresponding to an unresolved control instruction;
- and
- a controller configured to dispatch instructions from the instruction queue, and in response to a branch misprediction of the unresolved control instruction, to apply a selected one of a checkpointing-based recovery mode and a commit-time-based recovery mode.
Dependencies are inferred from the claim text.