Semiconductor device including row cache register

A device comprising:

• a memory cell array including a plurality of pages;
• a row cache register;
• and
• an array control circuit including a page address storage circuit that stores a row address supplied last time thereto, the array control circuit opening one of the pages selected based on the row address stored in the page address storage circuit and connecting the selected page to the row cache register in response to write command when none of the pages is opened.

A device comprising:

• an I/O line;
• a plurality of data lines including a first redundant data line and a first defective data line;
• a plurality of column switches each connected between an associated one of the data lines and the I/O line;
• a plurality of row cache registers each connected to an associated one of the data lines;
• a plurality of memory blocks each including a bit line and a plurality of word lines, one of the memory blocks being selected based on a block address which is a part of a row address;
• a plurality of transfer switches each connected between an associated one of the bit lines and an associated one of the data lines;
• and
• an array control circuit activating one of the word lines based on the row address and temporarily bringing one of the transfer switches related to the activated word line into an ON state, wherein
• the array control circuit includes:
• a first defective address information storage circuit storing first address information indicating a combination of a column address related to the first defective data line and the block address of one of the memory blocks related to the first defective data line;
• and
• a row address storage circuit storing at least the block address included in the row address supplied from outside,
• the array control circuit obtains second address information in response to a write command, the second address information indicating a combination of a column address supplied from outside along with the write command and the block address stored in the row address storage circuit,
• the array control circuit brings one of the column switches based on the column address supplied from outside into an ON state when the second address information does not coincide with the first address information stored in the first defective address information storage circuit,
• the array control circuit brings one of the column switches corresponding to the first redundant data line into an ON state when the second address information coincides with the first address information stored in the first defective address information storage circuit, and
• the array control circuit activates one of the word lines based on the row address and brings one of the transfer switches related to the activated word line into an ON state in response to the write command.