Flash memory device with multi-level cells and method of writing data therein
AssigneeSamsung Electronics Co., Ltd.
InventorsWon-Moon Cheon, Seon-Taek Kim, Chan-Ik Park, Sung-up Choi
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Abstract
In one aspect, a method of writing data in a flash memory system is provided. The flash memory system forms an address mapping pattern according to a log block mapping scheme. The method includes determining a writing pattern of data to be written in a log block, and allocating one of SLC and MLC blocks to the log block in accordance with the writing pattern of the data.
Claims21
A method of writing data in flash memory, the method comprising:
- receiving a write request related to write data;
- determining a writing pattern of the write data;
- and
- selectively allocating one of a first block and a second block to a log block in accordance with the determined writing pattern,
- wherein determining the writing pattern of the write data comprises at least one of determining whether the write data has a random-writing pattern by detecting discontinuous logical page addresses for the write data and determining whether the write data has a sequential-writing pattern by detecting continuous logical page addresses for the write data, and
- upon determining that the write data has the random-writing pattern, allocating the first block to the log block, and upon determining that the write data has the sequential-writing pattern, allocating the second block to the log block.
A method of writing data in multi-level cell (MLC) flash memory including a first MLC block and a second MLC block, the MLC flash memory operating in accordance with an address mapping pattern using a log block mapping scheme, the method comprising:
- determining whether a writing pattern of write data to be written in the MLC flash memory is a sequential-writing pattern or a random-writing pattern;
- and
- selectively allocating one of the first MLC block and the second MLC block to the log block in a write buffer in accordance with the writing pattern of the write data,
- wherein the sequential-writing pattern is determined according to continuous logical page addresses, and the random-writing pattern is determined according to discontinuous logical page addresses,
- the first MLC block includes only fast pages selected as available storage fields and the second MLC block includes both fast and slow pages selected as available storage fields, and
- at least one slow page of the second MLC block is allocated to the log block when the writing pattern of the write data is the sequential-writing pattern, and at least one fast page of at least one of the first MLC block and the second MLC block is allocated to the log block when the writing pattern of the write data is the random-writing pattern.
A memory system, comprising:
- a flash memory device including single-level cell (SLC) blocks and multi-level cell (MLC) blocks, each respectively capable of being used as a storage field for externally supplied write data;
- and
- a controller that detects a writing pattern of the write data, and selects at least one SLC block or at least one MLC block as a log block in accordance with the detected writing pattern of the write data,
- wherein a sequential-writing pattern is determined as the writing pattern for the write data upon identifying continuous logical page addresses, and a random-writing pattern is determined as the writing pattern for the write data upon identifying discontinuous logical page addresses, and
- the controller allocates at least one of the MLC blocks to the log block upon determining that the writing pattern of the write data is the sequential-writing pattern, and allocates at least one of SLC blocks to the log block upon determining that the writing pattern of the write data is the random-writing pattern.
Dependencies are inferred from the claim text.