Convenient, flexible, and efficient management of memory space and bandwidth

A non-transitory computer-readable medium storing instructions, the instructions comprising:

• one or more instructions that, when executed by a processor of a device, cause the processor to:
• receive a plurality of requests from a set of requestors, of a plurality of requestors, each request, of the plurality of requests, including an address,
• map, for each request, of the plurality of requests, a first set of bits of the address to a second set of bits of the address to form a modified address associated with the request,
• identify, for each request, of the plurality of requests, a memory bank, of a plurality of memory banks of a memory, based on a particular portion of the modified address,
• identify a set of requests, of the plurality of requests, that is associated with an available memory bank, of the plurality of memory banks,
• the one or more instructions to identify the set of requests including:
• one or more instructions to identify, based on a first priority, that the set of requests is associated with a highest quantity of different memory parts, of a plurality of memory parts, that include the plurality of memory banks,
• one or more instructions to identify, based on a second priority, that the set of requests is associated with a highest quantity of different requestors, and
• one or more instructions to identify, based on a third priority, that the set of requests is associated with a highest quantity of high priority requests,
• the first priority comprising a higher priority relative to the second priority, and
• the second priority comprising a higher priority relative to the third priority, and
• send, during a single clock cycle, each request, of the set of requests, to the identified memory bank associated with the request.

A method comprising:

• receiving a plurality of requests from a set of requestors, of a plurality of requestors, each request, of the plurality of requests, including an address;
• mapping, for each request, of the plurality of requests, a first set of bits of the address to a second set of bits of the address to form a modified address associated with the request;
• identifying, for each request, of the plurality of requests, a memory bank, of a plurality of memory banks of a memory, based on a particular portion of the modified address;
• identifying a set of requests, of the plurality of requests, that is associated with an available memory bank, of the plurality of memory banks,
• the identifying the set of requests including:
• identifying, based on a first priority, that the set of requests is associated with a highest quantity of different memory parts, of a plurality of memory parts, that include the plurality of memory banks,
• identifying, based on a second priority, that the set of requests is associated with a highest quantity of different requestors, and
• identifying, based on a third priority, that the set of requests is associated with a highest quantity of high priority requests,
• the first priority comprising a higher priority relative to the second priority, and
• the second priority comprising a higher priority relative to the third priority;
• and
• sending, during a single clock cycle, each request, of the set of requests, to the identified memory bank associated with the request.

A system comprising:

• one or more processors to:
• receive a plurality of requests from a set of requestors, of a plurality of requestors, each request, of the plurality of requests, including an address,
• map, for each request, of the plurality of requests, a first set of bits of the address to a second set of bits of the address to form a modified address associated with the request,
• identify, for each request, of the plurality of requests, a memory bank, of a plurality of memory banks of a memory, based on a particular portion of the modified address,
• identify a set of requests, of the plurality of requests, that are associated with an available memory bank, of the plurality of memory banks,
• when identifying the set of requests, the one or more processors being to:
• identify that the set of requests is associated with a highest quantity of different memory parts, of a plurality of memory parts, that include the plurality of memory banks,
• identify that the set of requests is associated with a highest quantity of different requestors, and
• identify that the set of requests is associated with a highest quantity of high priority requests, and
• send, during a single clock cycle, each request, of the set of requests, to the identified memory bank associated with the request.