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AssigneeAdvanced Micro Devices, Inc.
InventorsStephen D. Glaser, Mark D. Hummel
Estimating the term…
Methods and apparatus are provided for implementing a lightweight notification (LN) protocol in the PCI Express base specification which allows an endpoint function associated with a PCI Express device to register interest in one or more cachelines in host memory, and to request an LN notification message from the CPU/memory complex when the content of a registered cacheline changes. The LN notification message can be unicast to a single endpoint using ID-based routing, or broadcast to all devices on a given root port. The LN protocol may be implemented in the CPU complex by configuring a queue or other data structure in system memory for LN use. An endpoint registers a notification request by setting the LN bit in a “read” request of an LN configured cacheline.
A method of implementing a lightweight notification (LN) protocol in a central processing unit (CPU) memory complex having associated system memory, the method comprising:
A method of implementing a lightweight notification (LN) protocol in a host having a range of system memory designated for use as an LN data structure, said range comprising a plurality of cachelines each having a length of N bytes with an M<N byte subset of each cacheline reserved for LN storage, the method comprising:
A CPU complex configured to communicate with a PCIe endpoint device of the type including a lightweight notification request (LNR) module configured to send LN read and LN write request messages to the CPU complex, and to receive LN notification messages from the CPU complex, the CPU complex comprising:
Dependencies are inferred from the claim text.