Method and structure for inline electrical fin critical dimension measurement

A FinFET test circuit for electrically measuring the width of at least one fin of a FinFET, comprising:

• a plurality of gate test structures;
• and
• a doped fin test structure;
• wherein
• the plurality of gate test structures and the doped fin test structure are disposed on a substrate, wherein the width of the gates in the plurality of gate test structures are of at least two different widths.

A FinFET critical dimension test circuit comprising:

• a plurality of gate test structures;
• and
• a doped fin test structure;
• wherein
• the plurality of gate test structures and the doped fin test structure are disposed on a substrate;
• and wherein each gate test structure comprises:
• a doped silicon region;
• a gate dielectric layer disposed on the doped silicon region;
• and
• a gate disposed on the gate dielectric layer;
• and wherein the doped fin test structure comprises:
• a plurality of doped fins;
• a dielectric layer disposed over each of the plurality of fins;
• and
• a gate disposed over the plurality of fins;
• and wherein the critical dimension for each of the plurality of fins ranges from about 10 nanometers to about 15 nanometers.