Manufacturing method of flash memory structure with stress area

A manufacturing method of a flash memory structure with a stress area, comprising the steps of:

• providing a silicon substrate;
• forming two gate structures on the silicon substrate, wherein each of the two gate structure comprises a tunneling oxide layer, a floating gate, a dielectric layer and a control gate sequentially disposed on the silicon substrate, and the tunneling oxide layer is formed and deposited at 750° C.˜800° C. and processed with a thermal annealing process at 750° C.˜800° C.;
• comprehensively depositing a first oxide layer, a second oxide layer and a third oxide layer sequentially;
• etching to expose a top of the two gate structures;
• removing the third oxide layer between the two gate structures;
• forming a metal silicide layer on each of the two gate structures;
• comprehensively depositing a contact etch stop layer;
• and
• performing an anisotropic etching to expose the silicon substrate disposed between the two gate structures, such that the second oxide layer becomes an L-shaped spacer aligned towards one another and disposed between the two gate structures to form a first stress area, and a contact etch stop layer on each L-shaped spacer become a second stress area.