Three-dimensional semiconductor memory device

A method of forming a three-dimensional semiconductor memory device comprising:

• preparing a substrate comprising a pair of sub-cell regions and a strapping region between the pair of sub-cell regions;
• alternately forming sacrificial layers and dielectric layers on the substrate;
• patterning the dielectric layers and the sacrificial layers within the strapping region to form substantially symmetrical terraced structures in the strapping regions;
• forming a capping insulating layer covering the terraced structures of the sacrificial layers and dielectric layers;
• removing the sacrificial layers having the terraced structures to form empty regions;
• forming sub-gates in the empty regions, respectively, the sub-gates including a plurality of sub-gates stacked on the substrate in each of the pair of sub-cell regions, and each of the sub-gates including an extension extending laterally into the strapping region;
• and
• forming strapping lines electrically connected to the extensions of the stacked sub-gates, respectively,
• wherein the strapping lines includes at least a first strapping line and a plurality of second strapping lines;
• wherein the first strapping line is electrically connected to extensions of uppermost gates located in the pair of sub-cell regions, respectively;
• and
• wherein each of the plurality of second strapping lines is electrically connected to extensions of corresponding sub-gates, which are below the extensions of the uppermost gates and are disposed at the same level.