US 2013/0171789 A1 · METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Abstract

A method for manufacturing a semiconductor device includes providing a substrate having a first gate structure and a second gate structure formed thereon; blanketly forming a seal layer covering the first gate structure and the second gate structure on the substrate; performing a first ion implantation to form first light-doped drains (LDDs) in the substrate respectively at two sides of the first gate structure; and performing a second ion implantation to form second LDDs in the substrate respectively at two sides of the second gate structure; wherein at least one of the first ion implantation and the second ion implantation is performed to penetrate through the seal layer.

Claims20

Dependent claims

A method for manufacturing a semiconductor device comprising:

providing a substrate having a first gate structure and a second gate structure formed thereon;
blanketly forming a seal layer covering the first gate structure and the second gate structure on the substrate;
performing a first ion implantation to form first lightly-doped drains (LDDs) in the substrate respectively at two sides of the first gate structure;
performing a second ion implantation to form second LDDs in the substrate respectively at two sides of the second gate structure;
wherein at least one of the first ion implantation and the second ion implantation penetrates the seal layer.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

13/342,993Filed 4 Jan 2012

Published

4 Jul 2013

Term ends

Not estimatedThe source records don’t support an estimate.

Classification16 codes

H10D 84/017
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their source or drain regions, e.g. silicided source or drain regions
H10D 30/0212
Of FETs having insulated gates [IGFET]: using self-aligned silicidation
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 30/0275
Of lateral single-gate IGFETs: forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised…

Method for manufacturing semiconductor device

Life of this patent

Method for manufacturing semiconductor device

Life of this patent

Abstract

Claims20