Non-volatile memory device having vertical structure and method of manufacturing the same

A method of manufacturing a non-volatile memory device having a vertical structure, the method comprising:

• stacking a plurality of sacrificial layers and a plurality of interlayer insulating layers alternately on a substrate;
• forming a stacking structure by etching a first portion of the plurality of sacrificial layers and the interlayer insulating layers to form a plurality of sacrificial layer patterns and a plurality of interlayer insulating layer patterns,
• the plurality of sacrificial layer patterns and the plurality of interlayer insulating layer patterns defining first openings in the stacking structure that expose an upper portion of the substrate;
• forming semiconductor layer patterns in the first openings of the stacking structure;
• etching a second portion of the stacking structure to define a second opening in the stacking structure that is between the semiconductor layer patterns;
• etching the plurality of sacrificial layer patterns to define a plurality of rib grooves;
• and forming a plurality of gate patterns on the semiconductor layer patterns in the plurality of rib grooves,
• the plurality of gate patterns being recessed in a direction from a side wall of the plurality of interlayer insulating layer patterns to the semiconductor layer patterns.

A method of manufacturing a non-volatile memory device comprising:

• forming at least one stacked structure on a substrate, each stacked structure including,
• a semiconductor layer extending vertically on the substrate,
• a plurality of interlayer insulating layers extending a first distance from at least one sidewall of the semiconductor layer, the plurality of interlayer insulating layers being spaced apart to define grooves that expose a part of the at least one sidewall of the semiconductor layer,
• a storage layer in the grooves defined by the plurality of interlayer insulating layers, and
• a plurality of gate electrodes contacting the storage layer in the grooves defined by the plurality of interlayer insulating layers, the plurality of gate electrodes extending a second distance from the at least one sidewall of the semiconductor layer, the second distance being less than the first distance;
• and
• forming a bit line on the at least one stacked structure.