Non-volatile memory (nvm) and logic integration

A method of forming a non-volatile memory (NVM) cell and a logic transistor using a semiconductor substrate, comprising:

• forming a first high-k gate dielectric and a second high-k gate dielectric over the semiconductor substrate;
• forming a first work function setting metal on the first high-k gate dielectric and a second work function setting metal on the second high-k gate dielectric;
• forming a first dummy gate over the first work function setting metal and a second dummy gate over the second work function setting metal;
• forming a sidewall spacer around the second dummy gate;
• forming first source/drains in the substrate adjacent to the second dummy gate;
• forming a dielectric layer around the first dummy gate and the second dummy gate wherein a top surface of the dielectric layer is substantially aligned with a top surface of the first dummy gate and a top surface of the second dummy gate;
• removing the first dummy gate and the second dummy gate;
• replacing the first dummy gate with a select gate comprising a metal of a first type and the second dummy gate with a logic gate comprising a metal of the first type;
• forming a hard mask over the logic gate and the first source/drains;
• removing the dielectric layer from around the select gate while leaving the dielectric layer around the logic gate;
• forming a charge storage layer comprising nanocrystals over the semiconductor substrate;
• forming a metal layer over the charge storage layer;
• patterning the metal layer to form a control gate over a portion of the select gate and a portion of the substrate and removing the metal layer from over the hard mask;
• patterning the charge storage layer to leave a portion of the charge storage layer under the control gate and removing the charge storage layer over the hard mask;
• and
• forming second source/drains in the substrate adjacent to the select gate and control gate.

A method, comprising:

• forming a logic transistor having a metal logic gate over a logic work function setting metal, the logic work function setting metal on a high-k gate dielectric, a sidewall spacer around the metal logic gate, and silicided source/drains in a logic region of a semiconductor substrate and a metal select gate of a non-volatile memory (NVM) cell over an NVM work function setting metal, the NVM work function setting metal on a high-k dielectric and in an NVM region of the semiconductor substrate using a dielectric that is left around the metal logic gate and the metal select gate, wherein a top surface of the dielectric is substantially aligned to a top surface of the metal select gate and a top surface of the metal logic gate;
• removing the dielectric from around the metal select gate;
• forming a charge storage layer comprising nanocrystals over the logic region and the NVM region;
• forming a metal layer over the logic region and the NVM region;
• patterning the metal layer over the NVM region to form a metal control gate over a portion of the metal select gate and a portion of the substrate and removing the metal layer from the logic region;
• etching the charge storage layer to leave the charge storage layer under and aligned with the metal control gate and to remove the charge storage layer over the logic region;
• and
• forming source/drain regions in the substrate in the NVM region adjacent to the control gate and to the metal select gate.