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US 2013/0171785 A1Published application
Non-volatile memory (nvm) and logic integration
AssigneeFreescale Semiconductor, Inc.
InventorsMehul D. Shroff, Mark D. Hall
Life of this patent
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Abstract
A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A metal select gate of the NVM cell is formed over a high-k dielectric as is metal logic gate of a logic transistor. The logic transistor is formed, including forming source/drains, while the metal select gate of the NVM cell is formed. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region using metal nanocrystals and a metal control gate over a portion of the metal select gate and a portion of the charge storage region over the substrate. The charge storage region is etched to be aligned to the metal control gate.
Claims20
A method of forming an NVM cell and a logic transistor using a semiconductor substrate, comprising:
- in a non-volatile memory (NVM) region, forming over the semiconductor substrate a first high-k gate dielectric, a metal select gate, and a first dielectric layer, wherein the metal select gate is on the first high-k dielectric, a top surface of the first dielectric layer is substantially aligned with a top surface of the metal select gate, and the first dielectric layer has a first opening in which the metal select gate is present in the first opening;
- in a logic region, forming over the semiconductor substrate a second high-k gate dielectric, a metal logic gate, a source and a drain in the semiconductor substrate, and a second dielectric layer, wherein the metal logic gate is on the second high-k dielectric, a top surface of the second dielectric layer is substantially aligned with a top surface of the metal logic gate, and the second dielectric layer has a second opening in which the metal logic gate is present in the second opening;
- removing the first dielectric layer in the NVM region while leaving the second dielectric layer in the logic region;
- forming a charge storage layer comprising metal nanocrystals over the NVM region including over the metal select gate;
- forming a metal layer over the charge storage layer;
- patterning the metal layer to form a metal control gate;
- and
- etching the charge storage layer to leave a remaining portion of the storage layer aligned to the metal control gate.
5 more elements
A method of forming a non-volatile memory (NVM) cell and a logic transistor using a semiconductor substrate, comprising:
- forming a first dummy gate and a second dummy gate over a dummy gate dielectric;
- forming a sidewall spacer around the second dummy gate;
- forming first source/drains in the substrate adjacent to the second dummy gate;
- forming a dielectric layer around the first dummy gate and the second dummy gate wherein a top surface of the dielectric layer is substantially aligned with a top surface of the first dummy gate and a top surface of the second dummy gate;
- removing the first dummy gate and the second dummy gate;
- replacing the dummy dielectric with a high-k dielectric;
- replacing the first dummy gate with a select gate comprising a metal of a first type and the second dummy gate with a logic gate comprising a metal of the first type;
- forming a hard mask over the logic gate and the first source/drain regions;
- removing the dielectric layer from around the select gate while leaving the dielectric layer around the logic gate;
- forming a charge storage layer comprising metal nanocrystals over the semiconductor substrate;
- forming a metal layer over the charge storage layer;
- patterning the metal layer to form a control gate over a portion of the select gate and a portion of the substrate and removing the metal layer from over the hard mask;
- patterning the charge storage layer to leave a portion of the charge storage layer under the control gate and removing the charge storage layer over the hard mask;
- and
- forming second source/drains in the substrate adjacent to the select gate and control gate.
12 more elements
A method, comprising:
- forming a logic transistor having a metal logic gate, a high-k gate dielectric, a sidewall spacer around the metal logic gate, and silicided source/drains in a logic region of a semiconductor substrate and a metal select gate of a non-volatile memory (NVM) cell on a high-k dielectric and in an NVM portion of the semiconductor substrate using a dielectric that is left around the metal logic gate and the metal select gate, wherein a top surface of the dielectric is substantially aligned to a top surface of the metal select gate and a top surface of the metal logic gate;
- removing the dielectric from around the metal select gate;
- forming a charge storage layer comprising metal nanocrystals over the logic region and the NVM region;
- forming a metal layer over the logic region and the NVM region;
- patterning the metal layer over the NVM region to form a metal control gate over a portion of the metal select gate and a portion of the substrate and removing the metal layer from the logic region;
- etching the charge storage layer to leave the charge storage layer under and aligned with the metal control gate and to remove the charge storage layer over the logic region;
- and
- forming source/drain regions in the substrate in the NVM region adjacent to the metal control gate and to the metal select gate.
5 more elements
Dependencies are inferred from the claim text.