Patterning A Single Integrated Circuit Layer Using Automatically-Generated Masks And Multiple Masking Layers

A lithographic system for patterning an integrated circuit (IC) layer, the lithographic system comprising:

• a light source;
• and
• a mask set for patterning multiple masking layers using the light source, the mask set comprising:
• a first mask for defining only fine-line features in a first masking layer, wherein each fine-line feature has a dimension less than a wavelength of the light, and wherein a pitch of a fine-line pattern, which includes a set of the fine-line features, is less than or equal to the wavelength;
• a second mask for one of removing and designating for removal portions of the fine-line features, wherein the second mask includes bloated features, each bloated feature corresponding to a layout feature of a desired layout that is expanded only in directions along a critical dimension of that layout feature, and wherein at least one layout feature in the desired layout includes a fine-line feature and a coarse feature;
• and
• a third mask for defining a plurality of coarse features of the IC layer in a second masking layer formed over a patterned first masking layer, wherein at least one coarse feature is defined to connect two fine-line features.