Clock regeneration circuit and digital audio reproduction device
AssigneePanasonic Corporation
InventorShinetsu KATOU
Life of this patent
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Abstract
A frequency detection circuit of a clock regeneration circuit measures time which an input clock takes to change a predetermined number of times, and outputs a count value proportional to the time. A division ratio generation circuit truncates bits of the output of the frequency detection circuit by using a quantizer, and outputs the obtained value as a division ratio. A variable frequency divider divides a master clock by the division ratio output from the division ratio generation circuit, and outputs the obtained clock as a new clock. A high-quality clock having reduced jitter is regenerated, so that audio reproduction with high-quality sound is possible.
Claims6
A clock regeneration circuit for generating a new clock from an input clock, the clock regeneration circuit comprising:
- a frequency detection circuit configured to measure time which the input clock takes to change a predetermined number of times, and output a count value proportional to the time as an N-bit digital signal, where N is an integer equal to or greater than 2;
- a division ratio generation circuit including a quantizer and configured to truncate the N-bit digital signal to M bits, where M is an integer less than N, by the quantizer and output the truncated signal as a division ratio;
- and
- a variable frequency divider configured to divide a master clock by the division ratio, and output the divided clock as the new clock.
Dependencies are inferred from the claim text.