Shift register

A shift register including a plurality of unit circuits connected in multiple stages,

• wherein each of the unit circuits includes:
• an output unit having an output terminal, a first transistor which supplies a first voltage to the output terminal, and a second transistor which supplies a second voltage to the output terminal;
• a first signal generating unit configured to supply a first signal for switching the first transistor between conduction and non-conduction to a gate electrode of the first transistor, based on an input signal which is a signal provided from an output terminal of a unit circuit in a previous stage and a clock signal;
• and
• a second signal generating unit configured to supply a second signal for switching the second transistor between conduction and non-conduction to a gate electrode of the second transistor, based on the input signal and the clock signal,
• the first signal generating unit includes:
• a first capacitor;
• a third transistor having a gate electrode connected to a clock signal line to which a clock signal is provided, and which switches conduction and non-conduction between the gate electrode of the first transistor and one of electrodes of the first capacitor;
• a fourth transistor having a gate electrode connected to an input line to which the input signal is provided, and which switches conduction and non-conduction between the other of the electrodes of the first capacitor and the clock signal line;
• and
• a fifth transistor having a gate electrode connected to a reference power supply line, and which switches conduction and non-conduction between the one electrode of the first capacitor and the input line.