Clock phase adjustment for a low-latency fifo
AssigneeOracle International Corporation
InventorJianghui Su
Life of this patent
Estimating the term…
Abstract
In a clock-adjustment circuit, a phase-detection circuit receives a first clock associated with a first clock domain and a second clock associated with a second clock domain, and determines a phase relationship between the first clock and the second clock. Then, the phase-adjustment circuit in the clock-adjustment circuit adjusts a phase of the first clock relative to the second clock if the determined phase relationship is associated with a metastable range of a first-in first-out (FIFO) buffer that transfers data from the first clock domain to the second clock domain, thereby reducing latency associated with the FIFO buffer.
Claims20
A clock-adjustment circuit, comprising:
- a first clock signal associated with a first clock domain;
- a second clock signal associated with a second clock domain;
- a phase-detection circuit configured to receive the first clock signal and the second clock and to determine a phase relationship between the first clock signal and the second clock signal;
- and
- a phase-adjustment circuit configured to adjust a phase of the first clock signal relative to the second clock signal when the determined phase relationship is associated with a metastable range of a first-in first-out (FIFO) buffer that stores data which is being transferred from the first clock domain to the second clock domain, thereby reducing latency associated with the FIFO buffer.
A system, comprising a clock-adjustment circuit,
- wherein the clock-adjustment circuit includes:
- a first clock signal associated with a first clock domain;
- a second clock signal associated with a second clock domain;
- a phase-detection circuit configured to receive the first clock signal and the second clock signal and to determine a phase relationship between the first clock signal and the second clock signal;
- and
- a phase-adjustment circuit configured to adjust a phase of the first clock signal relative to the second clock signal when the determined phase relationship is associated with a metastable range of a first-in first-out (FIFO) buffer that stores data which is being transferred from the first clock domain to the second clock domain, thereby reducing latency associated with the FIFO buffer.
A method for adjusting a phase of a first clock signal relative to a second clock signal, wherein the method comprises:
- receiving the first clock signal associated with a first clock domain and the second clock signal associated with a second clock domain;
- determining, using a phase-detection circuit, a phase relationship between the first clock signal and the second clock signal;
- and
- adjusting, using a phase-adjustment circuit, the phase of the first clock signal relative to the second clock signal when the determined phase relationship is associated with a metastable range of a first-in first-out (FIFO) buffer that stored data which is being transferred from the first clock domain to the second clock domain, thereby reducing latency associated with the FIFO buffer.
Dependencies are inferred from the claim text.