Clock rate controller and method thereof and electronic device thereof
AssigneeC-Media Electronics Inc.
InventorsJUNG-FU LIAO, HUNG-CHI HUANG
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Abstract
An exemplary embodiment of the present disclosure illustrates a clock rate control method. Firstly, a usage of a first input first output (FIFO) buffer in an electronic device is detected. Then, whether the usage falls within a first specific interval is determined, wherein the first specific interval has a first upper limit value and a first lower limit value. When the usage is larger than the first upper limit value, a clock rate of the inner device of the electronic device is increased; when the usage is less than the first lower limit value, the clock rate is decreased.
Claims20
A clock rate control method, comprising:
- detecting a usage of a first-input-first-output (FIFO) buffer in an electronic device;
- determining whether the usage falls within a first specific interval, wherein the first specific interval has an upper limit value and a lower limit value;
- when the usage is larger than the first upper limit value, increasing a clock rate of an internal device of the electronic device;
- and
- when the usage is less than the first lower limit value, decreasing the clock rate.
A clock rate controller, comprising:
- a usage detection unit, electrically connected to a FIFO buffer of an electronic device, used to detect a usage of the FIFO buffer;
- and
- a speed up/down determining unit, electrically connected to the usage detection unit and an internal device of the electronic device, used to detect whether the usage falls within a first specific interval, wherein the first specific interval has an upper limit value and a lower limit value;
- wherein when the usage is larger than the first upper limit value, the speed up/down determining unit increases a clock rate of the internal device of the electronic device;
- when the usage is less than the first lower limit value, the speed up/down determining unit decreases the clock rate.
An electronic device, used to connect a host, comprising:
- a FIFO buffer, electrically connected to the host, used to store a plurality of packet from the host;
- a clock rate controller, electrically connected to the FIFO buffer, used to determines whether a usage of the FIFO buffer falls within a first specific interval, wherein the first specific interval has an upper limit value and a lower limit value;
- and
- an internal device, electrically connected to the clock rate controller and the FIFO buffer, used to process the packet from the FIFO buffer according to a clock rate;
- wherein when the usage is larger than the first upper limit value, the clock rate controller increases the clock rate;
- when the usage is less than the first lower limit value, the clock rate controller decreases the clock rate.
Dependencies are inferred from the claim text.