Ultra low power memory cell with a supply feedback loop configured for minimal leakage operation

A memory cell comprising:

• a first nMOS device having a gate, a source, and a drain;
• a first pMOS device having a gate, a source, and a drain;
• a second nMOS device having a gate, a source, and a drain;
• a second pMOS device having a gate, a source, and a drain;
• and
• an nMOS gating device having a gate, a source, and a drain,
• wherein the source of the second pMOS device, the drain of the second nMOS device, and the gates of the first nMOS and the first pMOS devices are connected together forming a storage node QB,
• wherein the source of the first pMOS device, the drain of the first nMOS device, and the gates of the second nMOS and the second pMOS devices are connected together forming a storage node Q,
• wherein the sources of the first and the second nMOS devices are connected to ground,
• wherein the drains of the first and the second pMOS devices are connected to the source of the gating device,
• wherein the drain of the nMOS gating device is connected to a supply voltage, and
• wherein the gate of the nMOS gating device is connected to the storage node QB.