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US 2013/0170308 A1Published application
Semiconductor memory test method and semiconductor memory
AssigneeFujitsu Semiconductor Limited
InventorsKaoru MORI, Yoshimasa YAGISHITA, Hajime AOKI
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Abstract
A first erase test is performed by applying an erase pulse to series of memory cells which are included in a memory cell array and which are divided into a plurality of groups until the appearance of a group for which the determination that erase is completed is made. A second erase test is performed on other series of memory cells including the series of memory cells on the basis of the number of erase pulses at the time of detecting a group for which the determination that erase is completed is made first.
Claims9
A semiconductor memory test method comprising:
- performing a first erase test by applying an erase pulse to series of memory cells which are included in a memory cell array and which are divided into a plurality of groups until appearance of a group for which the determination that erase is completed is made;
- and
- performing a second erase test on other series of memory cells including the series of memory cells on the basis of a number of erase pulses at the time of detecting a group for which the determination that erase is completed is made first.
A semiconductor memory comprising:
- a memory cell array;
- and
- a test control circuit which controls the semiconductor memory so as to perform a first erase test by applying an erase pulse to series of memory cells which are included in the memory cell array and which are divided into a plurality of groups until appearance of a group for which the determination that erase is completed is made and so as to perform a second erase test on other series of memory cells including the series of memory cells on the basis of a number of erase pulses at the time of detecting a group for which the determination that erase is completed is made first.
Dependencies are inferred from the claim text.