Memory architecture and design methodology with adaptive read
AssigneeSTMicroelectronics Pvt. Ltd.
InventorsNavneet GUPTA, Prashant DUBEY, ShaileshKumar PATHAK, Kaushik SAHA, Ashish KUMAR, R Sai KRISHNA
Life of this patent
Estimating the term…
Abstract
An embodiment of a sense amplifier includes a sense circuit and a monitor circuit. The sense circuit is configured to convert a first signal that corresponds to data stored in a memory cell into a second signal that corresponds to the data, and the monitor circuit is configured to indicate a reliability of the second signal. The monitor circuit allows, for example, adjusting a parameter of a memory in which the memory cell is disposed to increase the read accuracy, and may also allow recognizing and correcting an error due to an invalid second signal.
Claims53
A sense amplifier, comprising:
- a sense circuit configured to convert a first signal that corresponds to data stored in a memory cell into a second signal that corresponds to the data;
- and
- a monitor circuit configured to indicate a reliability of the second signal.
A read circuit, comprising:
- at least one sense amplifier, including:
- a sense circuit configured to convert a first signal that corresponds to data stored in a memory cell into a second signal that corresponds to the data;
- and
- a monitor circuit configured to generate a monitor signal that indicates a reliability of the second signal;
- and
- a sense-amplifier controller, including:
- a delay circuit configured to enable the at least one sense amplifier to convert the first signal into the second signal a delay time after commencement of a read operation;
- and
- a calibration circuit configured to adjust the delay time in response to the monitor signal.
An integrated circuit, comprising:
- at least one memory cell configured to store data;
- and
- a read circuit, including:
- at least one sense amplifier, including:
- a sense circuit configured to convert a first signal that corresponds to the stored data into a second signal that corresponds to the data;
- and
- a monitor circuit configured to generate a monitor signal that indicates a reliability of the second signal;
- and
- a sense-amplifier controller, including:
- a delay circuit configured to enable the at least one sense amplifier to convert the first signal into the second signal a delay time after commencement of a read operation;
- and
- a calibration circuit configured to adjust the delay time in response to the monitor signal.
A system, comprising:
- a first integrated circuit including:
- at least one memory cell configured to store data;
- and
- a read circuit, including:
- at least one sense amplifier, including:
- a sense circuit configured to convert a first signal that corresponds to the stored data into a second signal that corresponds to the data;
- and
- a monitor circuit configured to generate a monitor signal that indicates a reliability of the second signal;
- and
- a sense-amplifier controller, including:
- a delay circuit configured to enable the at least one sense amplifier to convert the first signal into the second signal a delay time after commencement of a read operation;
- and
- a calibration circuit configured to adjust the delay time in response to the monitor signal;
- and
- a second integrated circuit coupled to the first integrated circuit.
A method, comprising:
- converting a first data signal from a memory cell into a second data signal;
- and
- indicating whether the second data signal is valid.
A memory block comprising:
- at least one memory cell;
- a sense amplifier configured to carry out a sensing operation on the at least one memory cell and determine whether the sensing operation is valid.
A method, comprising:
- carrying out a sensing operation on at least one memory cell by a sense amplifier;
- and
- determining by the sense amplifier whether the sensing operation is valid.
A sense amplifier, comprising:
- sensing circuitry configured to carry out a sensing operation on at least one memory cell;
- and
- error detection circuitry configured to determine whether the sensing operation is valid.
A memory block, comprising:
- memory means for storing a value;
- sensing means for carrying out a sensing operation on the memory means and for determining whether the sensing operation is valid.
A sense amplifier, comprising:
- sensing means for carrying out a sensing operation on at least one memory cell;
- and
- error detection means for determining whether the sensing operation is valid.
Dependencies are inferred from the claim text.