Parallel test circuit and method of semiconductor memory apparatus
AssigneeSK hynix Inc.
InventorsBo Yeun KIM, Ji Eun JANG
Life of this patent
Estimating the term…
Abstract
A parallel test circuit of a semiconductor memory apparatus includes a memory bank which includes first and second sub banks having test global lines, respectively, and sharing a global line connected to each of the first and second sub banks. When a read command is applied during a test mode, the parallel test circuit compares data loaded in the global line to data loaded in the test global line of the second sub bank to attain a comparison result, compresses the comparison result to attain a compression signal, and outputs the compression signal as a test output signal to a pad.
Claims20
A parallel test circuit of a semiconductor memory apparatus, comprising:
- a memory bank which includes first and second sub banks having test global lines, respectively, and sharing a global line connected to each of the first and second sub banks,
- wherein, when a read command is applied during a test mode, the parallel test circuit compares data loaded in the global line to data loaded in the test global line of the second sub bank to attain a comparison result, compresses the comparison result to attain a compression signal, and outputs the compression signal as a test output signal to a pad.
A parallel test circuit of a semiconductor memory apparatus, comprising:
- a first sub bank connected to a pad by a global line;
- a second sub bank connected to the global line, wherein the second sub bank is disconnected from the global line and connected to a test global line when a read command is applied during a test mode;
- a compression unit configured to compare data loaded in the global line to data loaded in the test global line and output a compression signal;
- and
- an output unit configured to generate a test output signal in response to the compression signal when a strobe signal is activated, and output the generated test output signal to the pad.
A parallel test method of a semiconductor memory apparatus, comprising the steps of:
- collectively writing data applied to a pad into first and second sub banks through a global line, when a write command is applied;
- transmitting the data stored in the first sub bank to the global line and transmitting the data stored in the second sub bank to a test global line, when a read command is applied;
- comparing the data loaded in the global line to the data loaded in the test global line to arrive at a comparison result, and compressing the comparison result to arrive at a compression signal;
- and
- outputting the compression signal as a test output signal to the pad when a strobe signal is activated.
Dependencies are inferred from the claim text.