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US 2013/0170299 A1Published application
Sharing local control lines across multiple planes in a memory device
AssigneeMicron Technology, Inc.
InventorAaron Yip
Life of this patent
Estimating the term…
Abstract
Memory devices, methods for accessing a memory cell, and memory systems are disclosed. One such memory device includes a plurality of planes of memory cells. Each plane of memory cells includes series strings of memory cells that each have a select gate drain transistor. Control gates of corresponding select gates are coupled together by a shared local control line. Each of a plurality of global control lines are coupled to their corresponding local control line with only a single global select gate.
Claims31
A memory device comprising:
- a plurality of planes of memory cells, each plane having at least one series string of memory cells, each series string of memory cells having a local select gate wherein a control gate of each corresponding local select gate of the plurality of planes of memory cells is coupled to a local shared control line and only one global select gate is configured to control access for the local shared control line to a global control line.
A memory device comprising:
- a first vertical plane of memory cells, wherein the first vertical plane of memory cells comprises a first vertical string of memory cells coupled to a first select gate;
- and
- a second vertical plane of memory cells, wherein the second vertical plane of memory cells comprises a second vertical string of memory cells coupled to a second select gate,
- wherein the first and second select gates are coupled to a shared local control line and only one global select gate couples the shared local control line to a global control line.
1 more element
A method for accessing a select memory cell comprising:
- activating a select gate to couple a global control line to an associated local control line that is shared by a plurality of local select gates across a plurality of planes of memory cells, wherein the selected memory cell is one of the plurality of planes;
- and
- biasing an access line coupled to a control gate of the selected memory cell.
A system comprising:
- a controller configured to control the memory system;
- and
- a memory device coupled to the controller the memory device comprising:
- a plurality of vertical planes of memory cells, each plane having at least one series string of memory cells, each series string of memory cells having a local select gate wherein a control gate of each corresponding local select gate of the plurality of planes of memory cells is coupled to a local shared control line and only one global select gate is configured to control access for the local shared control line to a global control line.
1 more element
A system comprising:
- a controller configured to control the system;
- and
- a memory device coupled to the controller the memory device comprising:
- a first vertical plane of memory cells, wherein the first vertical plane of memory cells comprises a first vertical string of memory cells coupled to a first select gate;
- and
- a second vertical plane of memory cells, wherein the second vertical plane of memory cells comprises a second vertical string of memory cells coupled to a second select gate,
- wherein the first and second select gates are coupled to a first shared local control line and only a first global select gate couples the first shared local control line to a first global control line.
4 more elements
A memory device comprising:
- a plurality of vertical planes of memory cells, each plane having a plurality of vertical strings of memory cells, each vertical string coupled to a respective local select gate, control gates of each of the corresponding local select gates of each plane coupled to a corresponding local control line wherein each corresponding local control line is coupled to a corresponding global control line only through one corresponding global select gate.
Dependencies are inferred from the claim text.