Memory controller for multi-level memory device and error correcting method
AssigneeSamsung Electronics Co., Ltd.
InventorEUN-JIN YUN
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Abstract
Disclosed is an error correcting method of a memory controller which controls a nonvolatile memory device. The error correcting method includes judging whether first read data read from the nonvolatile memory device is correctable; reading second read data from the nonvolatile memory device when the first read data is uncorrectable; and correcting an error of the first read data based on error information of the second read data and error information of the first read data.
Claims20
In a memory system including a memory controller controlling a nonvolatile memory device having a memory cell array of multi-level memory cells (MLC), wherein the memory system includes an error correcting circuit (ECC) generating parity data capable of correcting “Q” erroneous bits in read data retrieved from the memory device, where Q is a natural number, a correction method, comprising:
- retrieving first read data from a plurality of the MLC commonly coupled to a word line in response to a read command;
- determining whether or not the first read data is correctable in view of first parity data generated by the ECC from the first read data;
- upon determining that the first read data is not correctable, reading second read data from the plurality of the MLC and obtaining error information for the second read data;
- and
- modifying at least one erroneous bit in the first read data based on the error information for the second read data and error information for the first read data.
A memory system, comprising:
- a memory controller configured to control operation of a nonvolatile memory device and including an error correcting circuit (ECC) that generates parity data capable of correcting “Q” erroneous bits in read data retrieved from the memory device, where Q is a natural number;
- and
- the nonvolatile memory device includes a memory cell array of multi-level memory cells (MLC),
- wherein the memory controller is further configured to retrieve first read data from a plurality of the MLC commonly coupled to a word line in response to a read command, determine whether or not the first read data is correctable in view of first parity data generated by the ECC from the first read data, upon determining that the first read data is not correctable reading second read data from the plurality of the MLC and obtaining error information for the second read data, and modifying at least one erroneous bit in the first read data based on the error information for the second read data and error information for the first read data.
Dependencies are inferred from the claim text.