Semiconductor memory device and operation method thereof
AssigneeSK hynix Inc.
InventorsJun-Rye RHO, Seok-Hwan CHOI
Life of this patent
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Abstract
A semiconductor memory device includes an information generation unit configured to convert positions of threshold voltages of memory cells in threshold voltage distributions based on determination voltages included in an overlapping portion between the threshold voltage distributions to generate a plurality of position information codes, and an error correction unit configured to sequentially receive the plurality of position information codes and perform an error correction operation for data of the memory cells.
Claims11
A semiconductor memory device comprising:
- an information generation unit configured to convert positions of threshold voltages of memory cells in threshold voltage distributions based on determination voltages included in an overlapping portion between the threshold voltage distributions to generate a plurality of position information codes;
- and
- an error correction unit configured to sequentially receive the plurality of position information codes and perform an error correction operation for data of the memory cells.
A semiconductor memory system comprising:
- a memory unit configured to convert positions of threshold voltages of memory cells in threshold voltage distributions into a plurality of position information codes in response to determination voltages included in an overlapping portion between the threshold voltage distributions and sequentially output the plurality of position information codes in response to a read command;
- an error correction unit configured to perform an error correction operation on the plurality of position information codes for data of the memory cells;
- and
- a control unit configured to generate the read command in response to an output signal of the error correction unit.
An operating method of a semiconductor memory device, comprising:
- setting a plurality of determination voltages in an overlapping portion between threshold voltage distributions;
- converting a position of a threshold voltage of a memory cell in the threshold voltage distributions into a plurality of position information codes based on the plurality of determination voltages;
- performing an error correction operation on one position information code among the plurality of position information codes, in response to a read command;
- and
- detecting whether data of the memory cell is normal or not, depending on a result from the performing of the error correction operation.
An operating method of a semiconductor memory device, comprising:
- setting first to third determination voltages in an overlapping portion between threshold voltage distributions, wherein the first to third determination voltages are in order from the lowest to the highest;
- determining a position of a threshold voltage of a memory cell in the threshold voltage distributions based on the second determination voltage to generate a first position information code;
- determining the position of the threshold voltage based on the first and third determination voltages to generate a second position information code;
- and
- sequentially receiving the first and second position information codes to perform an error correction operation for data of the memory cell.
Dependencies are inferred from the claim text.