High voltage tolerant row driver

A high voltage row driver circuit comprising:

• a first transistor configured to receive a first gate voltage (PG1), to be supplied by a first voltage bias (VP1), and to provide an output (WLS);
• a first set of two transistors including a second transistor and a third transistor, the second transistor connected in parallel with the first transistor and configured to be supplied with the first voltage bias (VP1), and the third transistor connected to the second transistor and configured to be supplied with a second voltage bias (VN1) and to receive a second gate voltage (NG1);
• a second set of two transistors connected to the first set of two transistors and including a fourth transistor connected to a fifth transistor, the fourth transistor configured to be supplied by a fourth voltage bias (VP2) and to receive a third gate voltage (PG2), and the fifth transistor configured to be supplied by fourth voltage bias (VN2) and to receive a fourth gate voltage (NG2);
• and
• a line connecting a first n-well of the third transistor to a second n-well of the fifth transistor supplied by a fifth voltage bias (VN3);
• wherein:
• one or more of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor comprise extended drain devices.

A high voltage row driver circuit comprising:

• a first transistor configured to receive a first gate voltage and having a first source and a first extended drain;
• a first set of two transistors connected to the first transistor and including a second transistor and a third transistor, the second transistor having a second source and a second extended drain, the third transistor having a third extended drain, the second source of the second transistor connected in parallel with the first source of the first transistor, the second extended drain of the second transistor connected to the third extended drain of the third transistor, the second transistor configured to be biased by the first voltage bias, and the third transistor configured to be biased by a second voltage bias and to receive a second gate voltage;
• and
• a second set of two transistors connected to the first set of two transistors, the second set of two transistors including a fourth transistor and a fifth transistor, the fourth transistor having a fourth extended drain, the fifth transistor having a fifth extended drain, the fourth extended drain of the fourth transistor connected to the fifth extended drain of the fifth transistor, the fourth transistor configured to be biased by a fourth voltage bias and to receive a third gate voltage, and the fifth transistor configured to be biased by a fifth voltage bias and to receive a fourth gate voltage;
• and
• wherein:
• the first transistor, the second transistor, and the fourth transistor share a common bulk;
• and
• the third transistor and the fifth transistor share another common bulk.