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US 2013/0170288 A1Published application
Dual port register file memory cell with reduced susceptibility to noise during same row access
AssigneeSTMicroelectronics Pvt. Ltd.
InventorsNishu KOHLI, Hiten ADVANI
Life of this patent
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Abstract
A memory cell is formed by storage latch having a true node and a complement node. The cell includes a write port operable in response to a write signal on a write word line to write data from write bit lines into the latch, and a separate read port operable in response to a read signal on a read word line to read data from the latch to a read bit line. The circuitry of the memory cell is configured to address voltage bounce at the complement node during reading of the memory (where the voltage bounce arises from a simultaneous write to another memory cell in a same row).
Claims27
A dual port memory cell, comprising:
- a latch circuit having a true node and a complement node;
- a true write bit line node;
- a complement write bit line node;
- a read bit line node;
- a write word line node;
- a read word line node;
- a true write port circuit coupled between the true write bit line node and true node;
- a complement write port circuit coupled between the complement write bit line node and complement node;
- a read port circuit coupled between the read bit line node and the complement node;
- and
- means for addressing voltage bounce at the complement node during reading of the memory, said voltage bounce arising from a simultaneous write to another memory cell in a same row.
8 more elements
A dual port memory cell, comprising:
- a latch circuit having a true node and a complement node;
- a true write bit line node;
- a complement write bit line node;
- a read bit line node;
- a write word line node;
- a read word line node;
- a true write port circuit coupled between the true write bit line node and true node and including a first transistor of a first conductivity type, said first transistor configured to be actuated by a write signal at the write word line node;
- a complement write port circuit coupled between the complement write bit line node and complement node and including a second transistor of the first conductivity type, said second transistor configured to be actuated by the write signal at the write word line node;
- and
- a read port circuit coupled between the read bit line node and the complement node and including a third transistor of a second conductivity type opposite the first conductivity type, said third transistor configured to be actuated by a signal output from the complement node, and a fourth transistor of the second conductivity type configured to be actuated by a read signal at the read word line node.
7 more elements
A dual port memory cell, comprising:
- a latch circuit having a true node and a complement node;
- a true write bit line node;
- a complement write bit line node;
- a read bit line node;
- a write word line node;
- a read word line node;
- a true write port circuit coupled between the true write bit line node and true node and including a first transistor configured to be actuated by a write signal at the write word line node;
- a complement write port circuit coupled between the complement write bit line node and complement node and including a second transistor configured to be actuated by the write signal at the write word line node;
- and
- a read port circuit coupled between the read bit line node and the complement node and including:
- a third transistor source-drain coupled between a lower voltage reference node and an intermediate node, and having a gate terminal coupled to the complement node of the latch circuit;
- a fourth transistor source-drain coupled between the read bit line node and the intermediate node, and having a gate terminal coupled to the read word line node;
- and
- a fifth transistor source-drain coupled between a higher voltage reference node and the intermediate node, and having a gate terminal coupled to the true node of the latch circuit.
11 more elements
A dual port memory cell, comprising:
- a latch circuit having a true node and a complement node;
- a true write bit line node;
- a complement write bit line node;
- a read bit line node;
- a write word line node;
- a read word line node;
- a true write port circuit coupled between the true write bit line node and true node and including a first transistor configured to be actuated by a write signal at the write word line node;
- a complement write port circuit coupled between the complement write bit line node and complement node and including a second transistor configured to be actuated by the write signal at the write word line node;
- and
- a read port circuit coupled between the read bit line node and the complement node and including:
- a third transistor source-drain coupled between a lower voltage reference node and an intermediate node, and having a gate terminal coupled to the complement node of the latch circuit;
- a fourth transistor source-drain coupled between the read bit line node and the intermediate node, and having a gate terminal coupled to the read word line node;
- a fifth transistor source-drain coupled between a higher voltage reference node and the intermediate node, and having a gate terminal coupled to the complement node of the latch circuit.
10 more elements
A memory cell, comprising:
- a storage latch having a true node and a complement node;
- a write port operable in response to a write signal on a write word line to write data from at least one write bit line into the latch;
- and
- a read port operable in response to a read signal on a read word line to read data from the latch to a read bit line;
- wherein circuitry of the memory cell is configured to address voltage bounce at the complement node during reading of the memory by said read port where said voltage bounce arises from a simultaneous write to another memory cell in a same row, and wherein said voltage bounce would produce an unintended change in state of the read bit line.
2 more elements
Dependencies are inferred from the claim text.