Decoupling capacitance calibration devices and methods for dram

A decoupling capacitance (decap) calibration method for a DRAM, comprising:

• providing a plurality of parallel decoupling capacitors with a voltage from a power supply, the plurality of capacitors exhibiting a plurality of different capacitance values;
• providing the plurality of capacitors with a plurality of respective bitstate inputs, the plurality of bitstate inputs independently turning on or off the individual capacitors;
• generating a reference voltage;
• comparing a voltage at an output of the plurality of capacitors with the reference voltage to enable generating a determination signal;
• and
• selectively updating the plurality of bitstate inputs in response to the determination signal.

A decoupling capacitance (decap) calibration device for a DRAM, comprising:

• a plurality of parallel decoupling capacitors configured to be electrically connected to a power supply at a point between the power supply and logic circuitry, the plurality of capacitors exhibiting a plurality of different capacitance values and being configured to independently turn on or off according to a plurality of inputs;
• decap calibration circuitry configured to update the plurality of inputs in response to a determination signal;
• and
• a voltage detector configured to detect a voltage at an output of the plurality of capacitors and to compare the output voltage to a reference voltage, the decap calibration device being configured to generate the determination signal in response to the voltage comparison.

A decoupling capacitance (decap) calibration device for a DRAM, comprising:

• a power supply and logic circuitry, the power supply being configured to provide a voltage to the logic circuitry;
• a plurality of switched, parallel decoupling capacitors electrically connected to the power supply at a point between the power supply and the logic circuitry, the plurality of capacitors exhibiting a plurality of different capacitance values and being configured to independently switch on or off according to a plurality of bitstate inputs;
• decap bitstate calibration circuitry configured to update the plurality of bitstate inputs in response to a determination signal;
• a voltage detector electrically connected to the power supply at a point between the plurality of capacitors and electrically connected to the decap bitstate calibration circuitry, the voltage detector being configured to detect a voltage at an output of the plurality of capacitors and to compare the output voltage to a reference voltage;
• and
• fail determination circuitry electrically connected between the voltage detector and the decap bitstate calibration circuitry, the fail determination circuitry being configured to generate the determination signal in response to the voltage comparison.