# US 2013/0170284 A1 · Arrays Of Vertically Stacked Tiers Of Non-Volatile Cross Point Memory Cells, Methods Of Forming Arrays Of Vertically Stacked Tiers Of Non-Volatile Cross Point Memory Cells, And Methods Of Reading A Data Value Stored By An Array Of Vertically Stacked Tiers Of Non-Volatile Cross Point Memory Cells

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- Number: US 2013/0170284 A1
- Document ID: US20130170284A1
- Status: Published application
- Kind: A1
- Application number: 13/777,083
- Filed: 2013-02-26
- Published: 2013-07-04
- Earliest claimed: 2010-04-22
- Assignees: Micron Technology, Inc.
- Inventors: Sanh D. Tang; Gurtej S. Sandhu
- Web page: https://patentgrep.com/patent/US20130170284A1

## CPC

- G11C 5/02: Disposition of storage elements, e.g. in the form of a matrix array
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 13/0002: {using resistive RAM [RRAM] elements}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0023: {Address circuits or decoders}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10D 88/00: Three-dimensional [3D] integrated devices
- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C 7/18: Bit line organisation; Bit line lay-out
- G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 2213/71: Three dimensional array
- G11C 2213/78: Array wherein the memory cells of a group share an access device, all the memory cells of the group having a common electrode and the access device being not part of a word line or a bit line driver
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of horizontally oriented global bit lines having local vertical bit line extensions extend through multiple of the tiers. Individual of the memory cells comprise multi-resistive state material received between one of the horizontally oriented word lines and one of the local vertical bit line extensions where such cross, with such ones comprising opposing conductive electrodes of individual memory cells where such cross. A plurality of bit line select circuits individually electrically and physically connects to individual of the local vertical bit line extensions and are configured to supply a voltage potential to an individual of the global horizontal bit lines. Other embodiments and aspects are disclosed.

## Claims

### Claim 1

An array of vertically stacked tiers of non-volatile cross point memory cells, comprising:
a plurality of horizontally oriented word lines within individual tiers of memory cells;
a plurality of horizontally oriented global bit lines having local vertical bit line extensions extending through multiple of the tiers of memory cells; and
individual of the memory cells comprising multi-resistive state material received between one of the horizontally oriented word lines and one of the local vertical bit line extensions where such cross, with such ones of the horizontally oriented word lines and local vertical bit line extensions comprising opposing conductive electrodes of individual memory cells where such cross, the horizontally oriented word lines at least where such cross being of a conductively filled C-shape in a vertical cross section with an outline of the C-shape comprising one conductive material with a central portion of the C-shape being filled with another conductive material of different composition from the one conductive material.

### Claim 2 (depends on 1)

The array of claim 1 wherein the one and another conductive materials are homogenous, respectively.

### Claim 3 (depends on 1)

The array of claim 1 wherein the one conductive material comprises platinum.

### Claim 4 (depends on 1)

The array of claim 1 wherein the one conductive material is of higher conductivity than the another conductive material.

### Claim 5 (depends on 1)

The array of claim 1 wherein the another conductive material extends laterally outward of the C-shape outline of the one conductive material.

### Claim 6

An array of vertically stacked tiers of non-volatile cross point memory cells, comprising:
a plurality of horizontally oriented word lines within individual tiers of memory cells;
a plurality of horizontally oriented global bit lines having local vertical bit line extensions extending through multiple of the tiers of memory cells; and
individual of the memory cells comprising multi-resistive state material received between one of the horizontal word lines and one of the local vertical bit line extensions where such cross, with such ones of the horizontal word lines and local vertical bit line extensions comprising opposing conductive electrodes of individual memory cells where such cross, the multi-resistive state material comprising a C-shape in a vertical cross section.

### Claim 7 (depends on 6)

The array of claim 6 wherein the multi-resistive state material extends continuously along individual of the local vertical bit line extensions through multiple of the tiers.

### Claim 8 (depends on 6)

The array of claim 6 wherein the multi-resistive state material comprises a C-shape in a horizontal cross section.

### Claim 9 (depends on 6)

The array of claim 6 wherein the local vertical bit line extensions laterally fill center volume the C-shape.

### Claim 10 (depends on 6)

The array of claim 6 wherein the local vertical bit line extensions are individually homogenous.

### Claim 11 (depends on 6)

The array of claim 6 wherein the individual horizontal global bit lines with the local vertical bit line extensions are homogenous.

### Claim 12 (depends on 6)

The array of claim 6 wherein,
the multi-resistive state material extends continuously along individual of the local vertical bit line extensions through multiple of the tiers;
the multi-resistive state material comprises a C-shape in a horizontal cross section; and
the local vertical bit line extensions laterally fill center volume the C-shapes.

### Claim 13

An array of vertically stacked tiers of non-volatile cross point memory cells, comprising:
a plurality of horizontally oriented word lines within individual tiers of memory cells;
a plurality of horizontally oriented global bit lines having local vertical bit line extensions extending through multiple of the tiers of memory cells; and
individual of the memory cells comprising multi-resistive state material received between one of the horizontal word lines and one of the local vertical bit line extensions where such cross, with such ones of the horizontal word lines and local vertical bit line extensions comprising opposing conductive electrodes of individual memory cells where such cross, the multi-resistive state material comprising a composite of two different composition materials, one of the two materials of the composite comprising a plurality of spaced blocks received along individual of the local vertical bit line extensions with individual of the spaced blocks being associated with individual of the memory cells, the other of the two materials of the composite being of C-shape in a horizontal cross section and extending continuously along individual of the local vertical bit line extensions through multiple of the tiers.

### Claim at position 14

14-44. (canceled)

### Claim 45 (depends on 1)

The array of claim 1 wherein the one and another conductive materials are non-homogenous, respectively.

### Claim 46 (depends on 1)

The array of claim 1 wherein at least one of the one and another conductive materials is homogenous.

### Claim 47 (depends on 1)

The array of claim 1 wherein at least one of the one and another conductive materials is non-homogenous.

### Claim 48 (depends on 1)

The array of claim 1 wherein the multi-resistive state material comprises a C-shape in a horizontal cross section.