Variable resistance memory device and method for fabricating the same
OwnerSeok-Pyo Song, Sung-Woong Chung +2inventors
InventorsSeok-Pyo Song, Sung-Woong Chung, Su-Ock Chung, Dong-Joon Kim
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Abstract
A variable resistance memory device includes a semiconductor substrate having an active area defined by an isolation layer extending in one direction, a gate line extending in another direction crossing the isolation layer through the isolation layer and the active area, a protective layer located over the gate line, a contact plug positioned in a partially removed space of the active area between the protective layers, and a variable resistance pattern coupled to a part of the contact plug.
Claims28
A variable resistance memory device comprising:
- a semiconductor substrate having an active area defined by an isolation layer extending in one direction;
- a gate line extending in another direction crossing the isolation layer through the isolation layer and the active area;
- a protective layer located over the gate line;
- a contact plug positioned in a partially removed space of the active area between the protective layers;
- and
- a variable resistance pattern coupled to a part of the contact plug.
A method for fabricating a variable resistance memory device, comprising:
- providing a semiconductor memory device having an active area defined by an isolation layer extending in one direction;
- forming a trench extending in a direction crossing the isolation layer by selectively etching the isolation layer and the active area;
- forming a gate line and a protective layer over the gate line in the trench;
- forming a contact hole by partially etching the active area between the protective layers;
- forming a contact plug in the contact hole;
- and
- forming a variable resistance pattern coupled to a part of the contact plug.
A semiconductor device, comprising:
- a variable resistance pattern configured to store data with non-volatility;
- a bit line configured to deliver data to/from the variable resistance pattern;
- a word line configured to control data delivery between the bit line and the variable resistance pattern, including a buried gate line located at a level under a top surface of semiconductor substrate;
- and
- a source line configured to supply operational voltage to the variable resistance pattern,
- wherein a physical distance between the word line and the variable resistance pattern is shorter than that between the word line and the bit line.
Dependencies are inferred from the claim text.