Semiconductor memory device

A semiconductor memory device, comprising:

• a memory cell array including plural memory cell layers stacked, each memory cell layer containing plural first lines, plural second lines intersecting said first lines, and plural memory cells provided at the intersections of said plural first lines and second lines, wherein a certain one of said memory cell layers shares said first lines or said second lines with another one adjacently located in the direction of stacking,
• wherein said memory cell has asymmetrical voltage-current characteristics on application of a voltage of a first polarity and on application of a voltage of a second polarity different from said first polarity,
• wherein said memory cell has a first state, and a second state and a third state of higher resistances than that in said first state, wherein said memory cell,
• (1) in said second state, makes a transition to said first state on application of a first voltage of said first polarity,
• (2) in said first state, makes a transition to said second state on application of a second voltage of said second polarity,
• (3) in said first state, makes a transition to said third state on application of a third voltage of said second polarity (the third voltage<the second voltage), and
• (4) in said third state, makes a transition to said first state on application of a fourth voltage of said first polarity (the fourth voltage<the first voltage).

A semiconductor memory device, comprising:

• a memory cell array including a memory cell layer, said memory cell layer containing plural first lines, plural second lines intersecting said first lines, and plural memory cells provided at the intersections of said plural first lines and second lines,
• wherein said memory cell includes stacked memory elements containing metal ions, each memory element having a first electrode close to said first line and a second electrode close to said second line,
• wherein said memory cell has a first state through a third state, which differ in accordance with the states of a filament extending from said first electrode toward said second electrode in said memory element, wherein said first state is a state in which the tip of said filament reaches said second electrode, wherein said second state is a state in which said filament is not formed substantially, wherein said third state is a state in which the tip of said filament locates at a middle position between said first electrode and said second electrode, wherein said memory cell,
• (1) in said second state, makes a transition to said first state on application of a first voltage of a first polarity defined when the potential on said second electrode is lower than the potential on said first electrode,
• (2) in said first state, makes a transition to said second state on application of a second voltage of a second polarity defined when the potential on said first electrode is lower than the potential on said second electrode,
• (3) in said first state, makes a transition to said third state on application of a third voltage of said second polarity (the third voltage<the second voltage), and
• (4) in said third state, makes a transition to said first state on application of a fourth voltage of said first polarity (the fourth voltage<the first voltage).