Back to results
US 2013/0170277 A1Published application
Encoded Read-Only Memory (ROM) Bitcell, Array, and Architecture
AssigneeBroadcom Corporation
InventorsMyron BUER, Dechang SUN, Duane JACOBSON, David William KNEBELSBERGER, Kevin LeCLAIR
Life of this patent
Estimating the term…
Abstract
Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory cell comprises a transistor having drain, source, and gate terminals; and a plurality of program nodes, with each of the program nodes charged to a pre-determined voltage and coupled to a respective one of a plurality of bit lines.
Claims20
A memory block, comprising:
- a first memory array, including a first memory cell;
- a second memory array, including a second memory cell;
- a first common pull down (CPD) line configured to access the first memory cell;
- a second CPD line configured to access the second memory cell;
- and
- a shared bit line set, coupled to the first memory array and the second memory array, configured to read the first memory cell and the second memory cell.
3 more elements
A memory having a plurality of rows of memory cells, comprising:
- a plurality of memory blocks, each including respective rows of the plurality of rows of memory cells of the memory,
- wherein each of the plurality of memory blocks comprises a dedicated respective bit line set, common pull down (CPD) line set, and block input/output (I/O) circuitry.
A memory cell, comprising:
- a transistor having drain, source, and gate terminals;
- and
- a plurality of program nodes, each of the plurality of program nodes charged to a pre-determined voltage,
- wherein at most one of the plurality of program nodes is coupled to the drain terminal of the transistor to program the memory cell to store at least one information bit.
1 more element
Dependencies are inferred from the claim text.