Content-Addressable Memory Architecture for Routing Raw Hit Lines Using Minimal Base Metal Layers

An integrated circuit comprising at least one content-addressable memory circuit, the at least one content-addressable memory circuit comprising:

• a plurality of core memory cells, each memory cell including storage logic operative to store data indicative of a logical state of the memory cell, and comparison logic operative to generate a local match signal indicative of a comparison between the stored data and a compare value supplied to the memory cell;
• a plurality of local match lines, each local match line being coupled with a corresponding one of the plurality of memory cells and being adapted to convey the local match signal generated by the corresponding one of the plurality of memory cells;
• and
• combination logic operative to receive respective local match signals generated by at least a subset of the plurality of memory cells and to generate, for each content-addressable memory word, an output word match signal having a value indicative of respective values of the local match signals generated by the subset of the plurality of memory cells;
• wherein the subset of the plurality of memory cells is organized into at least one block having a prescribed maximum word size that is limited as a function of available space for routing tracks used to convey the local match signals and to convey at least one word match signal in a base metal layer across the memory cells to a boundary of the integrated circuit to thereby provide external access to the at least one word match signal.

A method for providing external access to output word match signals corresponding to respective words in a content-addressable memory circuit, the content-addressable memory circuit including a plurality of core memory cells, each memory cell including storage logic for storing data indicative of a logical state of the memory cell and comparison logic for generating a local match signal indicative of a comparison between the stored data and a compare value supplied to the memory cell, a plurality of local match lines, each local match line being coupled with a corresponding one of the plurality of memory cells and being adapted to convey the local match signal generated by the corresponding one of the plurality of memory cells, and combination logic operative to receive respective local match signals generated by at least a subset of the plurality of memory cells and to generate, for each content-addressable memory word, an output word match signal having a value indicative of respective values of the local match signals generated by the subset of the plurality of memory cells, the method comprising the steps of:

• determining, for a given integrated circuit process used to fabricate the content-addressable memory circuit, an amount of space available for routing tracks used to convey the local match signals and to convey the output word match signal in a base metal layer across the memory cells to a boundary of an integrated circuit in which the content-addressable memory circuit is formed;
• determining a maximum word block size for the content-addressable memory circuit as a function of the determined amount of space available for routing tracks;
• combining a plurality of blocks of memory cells using the combination logic, each of the plurality of blocks having a word size associated therewith that is less than or equal to the maximum word block size, to thereby generate the output word match signal for a corresponding word in the content-addressable memory circuit;
• routing output word match signals corresponding to respective words in the content-addressable memory circuit using base metal layer tracks across the memory cells to a boundary of an integrated circuit in which the content-addressable memory circuit is formed to thereby provide external access to the output word match signals.